| Our Publications and Patents |
Journal papers
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Unroll-based Copy Elimination for Enhanced Pipeline Scheduling
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S. Kim, S.-M. Moon, J. Park, K. Ebcioglu
To appear in IEEE Transactions on Computers.
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Dynamic Binary Translation and Optimization
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K. Ebcioglu, E.R. Altman, M. Gschwind, S. Sathaye
IEEE Transactions on Computers, Volume 50, Issue 6, pp. 529 - 548, June 2001.
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Advances and Future Challenges in Binary Translation and
Optimization
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E.R. Altman, K. Ebcioglu, M. Gschwind, S. Sathaye
Proceedings of the IEEE, Special Issue on Microprocessor Architecture
and Compiler Technology, pp. 1710-1722, November 2001.
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Welcome to the Opportunities of Binary Translation
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E.R. Altman, D. Kaeli, Y. Sheffer
IEEE Computer, Volume 33, Issue 3,
pp. 40-45, March, 2000.
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Dynamic and Transparent Binary Translation
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M. Gschwind, E.R. Altman, S. Sathaye, P. Ledak, D. Appenzeller
IEEE Computer, Volume 33, Issue 3,
pp. 54-59, March, 2000.
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A Just-in-Time Compiler
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Soo-Mook Moon and Kemal Ebcioglu
IEEE Computer, Volume 33, Issue 3,
pp. 41 (sidebar), March, 2000.
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The Performance Impact of Exploiting Branch ILP with Tree
Representation of ILP Code
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S.M. Moon, K. Ebcioglu
The Computer Journal (British Computer Society), 41(1), pp. 26-44, 1998.
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Parallelizing Non-Numerical Code with
Selective Scheduling and Software Pipelining
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S.M. Moon, K. Ebcioglu
ACM Transactions on
Programming Languages and Systems, November 1997, Vol. 19,
No. 6, pp. pp. 853-898, ACM Press.
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Compilers for Instruction-level Parallelism
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M. Schlansker (HP), T.M. Conte (North Carolina State U.), J. Dehnert
(SGI), K. Ebcioglu (IBM), J.Z. Fang (Intel), C.L. Thompson (HP).
IEEE Computer Magazine 30(12), December 1997,
pp. 63-69.
- Simulation/evaluation environment for a VLIW
processor architecture
- J.H. Moreno, M. Moudgill, K. Ebcioglu, E.R. Altman, B. Hall,
R. Miranda, S.K. Chen, A. Polyak
IBM Journal of Research and Development, Vol. 41, No. 3, May 1997, pp.287-302.
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Making Compaction Based Parallelization Affordable
- T. Nakatani, K. Ebcioglu
IEEE Transactions on Parallel and Distributed
Systems, Vol. 4, No. 9, pp. 1014-1029, September 1993.
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An Architectural Framework for Supporting Heterogeneous Instruction-Set
Architectures
- G.M. Silberman, K. Ebcioglu
IEEE Computer, vol. 26, no. 6, pp. 39-56, June 1993.
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Selective scheduling framework for speculative operations in VLIW and
superscalar processors
- S.M. Moon, K. Ebcioglu, A.K. Agrawala (Univ. of Md. at College
Park)
Information Processing Transactions, vol.23, pp.229-242, 1993.
- On Optimal Parallelization of Arbitrary Loops
- U. Schwiegelshohn, F. Gasperoni, K. Ebcioglu
Journal of Parallel and Distributed Computing, vol. 11,
pp.130-134, Academic Press, 1991.
- A Wide Instruction Word Architecture for Parallel
Execution of Logic Programs Coded in BSL
- K. Ebcioglu, M. Kumar
New Generation Computing, vol. 7, pp. 219-242, Omsha
Ltd. and Springer-Verlag, 1990.
Conference Papers
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Precise Exceptions in Dynamic Optimization
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M. Gschwind, E.R. Altman
Proc. 2002 Symposium on Compiler Construction, (CC 2002), Grenoble,
France, April 2002.
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Prolog Tailoring Technique on an Epilog Tailored Procedure
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Y.-C. Jhi, K.-C. Kim, K. Ebcioglu, Y. S. Lee.
Lecture Notes in Computer Science, Vol. 2244, pp. 424-436, December 2001.
(presented in Andrei Ershov Fourth International Conference on Perspectives on System Informatics, 2 - 6 July 2001, Novosibirsk, Akademgorodok, Russia.)
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CARS: A New Code Generation Framework for Clustered ILP Processors
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K. Kailas, K. Ebcioglu, and A. Agrawala
Proc. Seventh International Symposium on High Performance Computer
Architecture (HPCA-7), pp. 133-143, Monterrey, Mexico, January 2001.
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Simulation and Debugging of Full System Binary Translation
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E. R. Altman and K. Ebcioglu
Proceedings of the International
Society for Computers and Their Applications 13th International Conference,
Las Vegas, Nevada, USA, August 8-10, 2000, pp. 446-453, Editors: G. Chaudhry
and E. Sha, ISBN: 1-880843-34-X.
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Efficient Java Exception Handling in Just-in-Time Compilation
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S.I. Lee, B.S.
Yang, S. Kim, S. Park, S.M. Moon, K. Ebcioglu, and E. Altman
Proc. ACM 2000 Java Grande Conference, San Francisco,
California, June, 2000.
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Unroll-based Register Coalescing
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S. Kim, S.M. Moon, J. Park, and K. Ebcioglu
Proc. International Conference on Supercomputing 2000,
May 2000, Santa Fe, New Mexico, pp. 296-305, ACM press.
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Binary Translation and Architecture Convergence Issues for IBM S/390
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M. Gschwind, K. Ebcioglu, E. Altman, and S. Sathaye
Proc. International Conference on Supercomputing 2000,
May 2000, Santa Fe, New Mexico, pp. 336-347, ACM press.
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Reducing Sweep Time for a Nearly Empty Heap
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Y.C. Chung, S. M. Moon, K. Ebcioglu, and D. Sahlin
Proc. 27th Annual ACM SIGPLAN-SIGACT Symposium on
Principles of Programming Languages (POPL '00),
Boston, Massachusetts, January 2000.
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Optimizations and Oracle Parallelism with Dynamic Translation
[Abstract and foils]
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K. Ebcioglu, E.R. Altman, S. Sathaye, and M. Gschwind
Proc. MICRO-32, Haifa, Israel, November 1999.
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LaTTe: A Java VM Just-in-Time Compiler with Fast and Efficient
Register Allocation,
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B.S. Yang, S.M. Moon, S. Park, J. Lee, S. Lee,
J. Park, Y. C. Chung, S. Kim, K. Ebcioglu, E. Altman.
Proc. PACT '99, pp. 128-138,
IEEE Computer Society Press, October 1999.
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Execution-Based
Scheduling for VLIW Architectures
[Abstract and foils]
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K. Ebcioglu, E. Altman, S. Sathaye, M. Gschwind,
Proc. Europar '99 (P. Amestoy, P.
Berger, M. Dayde, I. Duff, V. Fraysse, L. Giraud, D. Ruiz, eds.), pp.
1269-1280, Lecture Notes in Computer Science 1685, Springer-Verlag
1999.
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An Eight-Issue Tree VLIW Processor for Dynamic
Binary Translation.
[Abstract]
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K. Ebcioglu, J. Fritts, S. Kosonocky, M. Gschwind, E. Altman, K.
Kailas, and T. Bright
Proc. ICCD-98, Dallas, TX, 1998.
- Scalable instruction-level parallelism through
tree-instructions
- J.H. Moreno, M. Moudgill
1997 International Conference on Supercomputing
Vienna, Austria, July 7-11, 1997, pp. 1-11.
- Performance Analysis of a Tree VLIW Architecture for Exploiting
Branch ILP in Non-numerical Code
- S.M. Moon, K. Ebcioglu
1997 International Conference on Supercomputing
Vienna, Austria, July 7-11, 1997, pp. 301-308.
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DAISY: Dynamic Compilation for 100% Architectural Compatibility
- K. Ebcioglu, E.R. Altman
24th Annual International Symposium on Computer Architecture
Denver, Colorado, June 2-4, 1997, pp. 26-37.
IBM Research Report RC20538, August, 1996
[fulltext]
(This is an extended version of the ISCA paper.)
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VLIW Compilation Techniques in a Superscalar Environment
- K. Ebcioglu, R. Groves, K.C. Kim, G. Silberman, I. Ziv
Proc. PLDI-94, ACM SIGPLAN Notices, vol. 29, no. 6, pp. 36-48, June 1994.
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On Performance and Efficiency of VLIW and Superscalar
- S.M. Moon, K. Ebcioglu
in International Conference on Parallel Processing, vol. 2,
pp. 283-287, 1993, CRC Press, Ann Arbor.
- A Study on the Number of Memory Ports in Multiple
Instruction Issue Machines
- S.M. Moon, K. Ebcioglu
in Proceedings of MICRO-26, IEEE Press, 1993.
- An Efficient Resource-Constrained Global Scheduling
Technique for Superscalar and VLIW Processors
- S.M. Moon, K. Ebcioglu
in Proceeding of MICRO-25, pp. 55-71, IEEE Press, December 1992.
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An Architectural Framework for Migration from CISC
to Higher Performance Platforms
- G.M. Silberman, K. Ebcioglu
in Proceedings of International Conference on Supercomputing,
pp. 198-215, ACM Press, 1992.
- Using a Lookahead Window in a Compaction based
Parallelizing Compiler
- T. Nakatani, K. Ebcioglu
in Proceedings of MICRO-23, pp. 57-68, IEEE Press, 1990.
- A New Compilation Technique for Parallelizing Loops
with Unpredictable Branches on a VLIW Architecture
- K. Ebcioglu, T. Nakatani
in Languages and Compilers for Parallel Computing, D. Gelernter,
A. Nicolau, D. Padua (eds.), Research Monographs in Parallel and
Distributed Computing, pp. 213-229, MIT Press, 1990.
- Combining as a Compilation Technique for VLIW
Architectures
- T. Nakatani, K. Ebcioglu
in Proceedings of MICRO-22, pp. 43-55, ACM Press, 1989.
- On Optimal Loop Parallelization
- U. Schwiegelshohn, F. Gasperoni, K. Ebcioglu
in Proceedings of MICRO-22, pp. 141-146, ACM Press, 1989.
- A Global Resource-constrained Parallelization
Technique
- K. Ebcioglu, A. Nicolau
in Proceedings Third International Conference on Supercomputing,
pp. 154-163, Crete, June 1989.
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A Wide Instruction Word Architecture for Fine-Grain
Parallelism
- K. Ebcioglu
in Proceedings CONPAR-88, C.R. Jesshope, K.D. Reinartz (eds.),
pp. 424-434, Cambridge University Press, 1989.
- A Wide Instruction Word Architecture for Parallel
Execution of Logic Programs Coded in BSL
- K. Ebcioglu, M. Kumar
Proceedings of the International Conference on Fifth Generation Computer Systems, 1988,
pp. 931-942. Edited by ICOT, Japan.
- Some Design Ideas for a VLIW Architecture for Sequential
Natured Software
- K. Ebcioglu
in Proceedings of IFIP WG 10.3 Working Conference
on Parallel Processing, pp. 3-21, M. Cosnard et al. (eds.),
North Holland, 1988.
- A Compilation Technique for Software Pipelining of Loops
with Conditional Jumps
- K. Ebcioglu
in Proceedings of MICRO-20, pp. 69-79, ACM Press, December 1987.
Workshop Papers
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Inherently Lower Complexity Architectures using Dynamic Optimization
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M. Gschwind, E.R. Altman
Proc. Workshop on Complexity Effective Design in conjunction with
ISCA-2002,
Anchorage, AK, May 2002.
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Optimization and Precise Exceptions in Dynamic Compilation
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M. Gschwind, E.R. Altman
Proc. Workshop on Binary Translation 2000 (WBT-2000),
Philadelphia, PA, October 2000.
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Reducing Virtual Call Overheads in a Java VM Just-in-Time
Compiler
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J. Lee, B.S. Yang, S. Kim, S. Lee, Y. C. Chung, H. Lee, J.H. Lee,
S.M. Moon, K. Ebcioglu, and E. Altman
1999 Workshop on Interaction between Compilers and
Computer Architectures, Toulouse, France, January 2000.
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On-Demand Translation of Java Exception
Handlers in the LaTTe JVM Just-in-Time Compiler
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S. I. Lee, B.S. Yang, S. Kim, S. Park, S.M. Moon,
K. Ebcioglu, E. Altman
1999 Workshop on
Binary Translation (Binary99), New Port Beach, California, October
1999
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BOA: Targeting Multi-Gigahertz with Binary Translation
[ Foils ]
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S. Sathaye, P. Ledak, J. LeBlanc, S. Kosonocky, M. Gschwind, J.
Fritts, Z. Filan, A. Bright, D. Appenzeller, E. Altman, and C. Agricola
1999 Workshop on
Binary Translation (Binary99), New Port Beach, California, October
1999
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Constant Value Prediction in VLIW Machines through Dynamic
Compilation
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H.M. Chung, S.M. Moon, K. Ebcioglu
1999 Workshop on
Binary Translation (Binary99), New Port Beach, California, October
1999
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Lightweight
Monitor in Java Virtual Machine
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B.S. Yang, J. Lee, J. Park, S.M. Moon, and K. Ebcioglu.
ACM Computer Architecture News, March 1999.
Also in proceedings of the Third Workshop on
Interaction Between Compilers and Computer Architectures (INTERACT-3).
In conjunction with ASPLOS-VIII, San Jose, CA, October 1998.
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Implementing an Experimental VLIW Compiler
- M. Moudgill
IEEE Technical Committee on Computer Architecture Newsletter
June 1997, pp. 39-40.
Also in proceedings of the
Workshop on Computer Architecture Education,
1997 High-Performance Computer Architecture Conference (HPCA97),
San Antonio, February 1997.
- Compiler/architecture interaction in a tree-based VLIW
processor
- M. Moudgill, J.H. Moreno, K. Ebcioglu, E.R. Altman, S.K. Chen, A. Polyak
IEEE Technical Committe on Computer Architecture Newsletter
June 1997, pp. 10-12.
Also in proceedings of the
Workshop on Interaction between Compilers and Computer Architectures,
1997 High-Performance Computer Architecture Conference (HPCA97),
San Antonio, February 1997.
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A JAVA ILP Machine Based on Fast Dynamic Compilation [fulltext]
- K. Ebcioglu, E.R. Altman, E. Hokenek
IEEE MASCOTS International Workshop on Security and Efficiency Aspects
of Java
Eilat, Israel, January 9-10, 1997
Research Reports
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High Frequency Pipeline Architecture Using the Recirculation
Buffer [fulltext]
- Michael Gschwind, Stephen Kosonocky, Erik Altman
IBM Research Report RC 23113, March 2001
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Dynamic Binary Translation and Optimization [fulltext]
- K. Ebcioglu, E. Altman, M. Gschwind, S. Sathaye
IBM Research Report RC 22025, July 2000
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BOA: The Architecture of a Binary Translation Processor [fulltext]
- E. Altman, M. Gschwind, S. Sathaye, S. Kosonocky, A. Bright, J. Fritts,
P. Ledak (IBM Burlington), D. Appenzeller (IBM Burlington), C. Agricola (IBM Burlington),
Z. Filan (IBM Burlington)
IBM Research Report RC 21665, December 1999
- Efficient Instruction scheduling with precise exceptions [fulltext]
- E. Altman, K. Ebcioglu, M. Gschwind, S. Sathaye
IBM Research Report RC22957, December 1999
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DAISY/390: Full System Binary Translation of IBM System/390 [fulltext]
- M. Gschwind, K. Ebcioglu, E. Altman, S. Sathaye
IBM Research Report RC 22027, June 1999
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Run-time detection and recovery from incorrectly reordered memory
operations [fulltext]
- M. Moudgill, J.H. Moreno
IBM Research Report RC 20857, November 1997
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ForestaPC User Instruction Set Architecture
[fulltext]
- J.H.Moreno, K. Ebcioglu, M. Moudgill, D. Luick
IBM Research Report RC20733, February 1997
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Dynamic translation of tree-instructions into VLIWs [fulltext]
- Jaime H. Moreno
IBM Research Report RC20505, July 1996
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Architecture, compiler and simulation of a tree-based VLIW
processor [fulltext]
- J.H. Moreno, M. Moudgill, K. Ebcioglu, E.R. Altman, B. Hall,
R. Miranda, S.K. Chen, A. Polyak
IBM Research Report RC20495, July 1996
- Some Global Compiler Optimizations and Architectural
Features for Improving Performance of Superscalars
- K. Ebcioglu, R. Groves
IBM Research Report RC16145, 1990.
Technical disclosures and research publications
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Method and apparatus for determining branch
addresses in programs generated by binary translation
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M. Gschwind
IBM Invention Disclosure YOR8-1998-0334, Yorktown Heights, NY,
July 1998. Research Disclosures, no. 416, December 1998.
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Method and apparatus for rapid return address determination in
binary translation
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M. Gschwind
IBM Invention Disclosure YOR8-1998-0410, Yorktown Heights, NY,
September 1998.
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Method for the deferred materialization of condition code information
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M. Gschwind
IBM Invention Disclosure YOR8-1999-0001, Yorktown Heights, NY,
January 1999. Research Disclosures, no. 431, March 2000.
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Method for achieving high hit rate for an address translation cache in
binary translation
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M. Gschwind
IBM Invention Disclosure YOR8-1999-0194, Yorktown Heights, NY,
March 1999. Research Disclosures, no. 431, March 2000.
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Method for implementing precise exceptions
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M. Gschwind
IBM Invention Disclosure YOR8-1999-0197, Yorktown Heights, NY,
March 1999. Research Disclosures, no. 431, March 2000.
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Method and apparatus for the selective scoreboarding of computation results
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M. Gschwind
IBM Invention
Disclosure YOR8-2000-0004, Yorktown Heights, NY, January 2000. IBM
Technical Disclosure Bulletin 2001-01.
US Patents
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Method and apparatus for implementing execution predicates in a computer processing system
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M. Gschwind, S. Sathaye
1/28/2003 Issued as US patent 6513109
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Method and apparatus for reordering memory operations along multiple execution paths in a processor
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E. Altman, M. Gschwind
04/30/2002 Issued as US patent 6381691
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Methods and apparatus for reordering and renaming memory references in a multiprocessor computer system
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E. Altman, K. Ebcioglu, M. Gschwind, S. Sathaye
02/19/2002 Issued as US patent 6349361
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Pipeline control for high-frequency pipelined designs
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M.K. Gschwind
02/20/2000 Issued as US patent 6192466
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Forwarding stored data fetched for out-of-order load/read operation
to over-taken operation read-accessing same memory location
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M.K. Gschwind
02/13/2000 Issued as US patent 6189088
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Method and apparatus to select the next instruction in a
superscalar or a very long instruction word computer having
n-way branching
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K. Ebcioglu,
K.J. Kiefer,
D.A. Luick,
G.M. Silberman,
P.B. Winterfield
08/29/00 Issued as US patent 6112299
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Object code compatible representation of very long instruction word programs
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J.H. Moreno
09/14/99 Issued as US patent 5951674 (as continuation of US patent 5669001)
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Apparatus for region-based detection of interference among
reordered memory operations in a processor
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J.H. Moreno, M. Moudgill
06/29/99 Issued as US patent 5918005
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Handling of exceptions in speculative instructions
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K. Ebcioglu, G.M. Silberman
08/25/98 Issued as US patent 5799179
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Method and apparatus for reordering memory operations in a processor
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J.H. Moreno, M. Moudgill
05/26/98 Issued as US patent 5758051
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Method and apparatus for dynamic conversion of computer
instructions
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K. Ebcioglu, R.D. Groves
02/24/98 Issued as US patent 5721854
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Object code compatible representation of very long instruction word programs
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J.H. Moreno
09/16/97 Issued as US patent 5669001
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Method and apparatus for reordering memory operations in a
superscalar or very long instruction word processor
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K. Ebcioglu,
D.A. Luick,
J.H. Moreno,
G.M. Silberman,
P.B. Winterfield
04/29/97 Issued as US patent 5625835
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Method and apparatus for improving performance of out of
sequence load operations in a computer system
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K. Ebcioglu, E. Kronstadt, M. Kumar
07/30/96 Issued as US patent 5542075
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Virtual multi-port ram employing multiple accesses during single
machine cycle
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B.A. Chappell, T.I. Chappell, K. Ebcioglu, S.E. Schuster
07/30/96 Issued as US patent 5542067
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General-purpose memory access scheme using register-indirect
mode
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C. Chuang, K. Ebcioglu
11/22/94 Issued as US patent 5367648
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Virtual multi-port ram
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B.A. Chappell, T.I. Chappell, K. Ebcioglu, S.E. Schuster
04/20/93 Issued as US patent 5204841
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