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Volume 36, Number 2, 1997
S/390 Parallel Sysplex Cluster
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S/390 cluster technology: Parallel Sysplex - Author bios

by J. M. Nick, B. B. Moore, J.-Y. Chung, and N. S. Bowen

Biographical sketches of authors

Jeffrey M. Nick IBM S/390 Division, 522 South Road, Poughkeepsie, New York 12601 (electronic mail: jeff_nick@vnet.ibm.com). Mr. Nick is a Senior Technical Staff Member working in the OS/390 System Architecture and Design area. He joined IBM in 1980 as a developer in the S/390 MVS operating system. During his career at IBM, he has held positions in MVS system design and development, and as a large systems technical specialist focused on continuous availability issues. Mr. Nick has lead architecture responsibility for the design of S/390 parallel processing technology and is presently focused on leveraging that technology for new application environments on the OS/390 platform. He is widely recognized as a leading technical expert on S/390 Parallel Sysplex. He received a Corporate Award for his contribution in the design and development for the Parallel Sysplex coupling facility. Mr. Nick currently has 18 patents in the field of operating systems technology and has published several papers in technical journals. He has also given tutorials on the Parallel Sysplex worldwide.

Brian B. Moore IBM S/390 Division, 522 South Road, Poughkeepsie, New York 12601 (electronic mail: bbmoore@vnet.ibm.com). Dr. Moore is a Senior Technical Staff Member and member of the IBM Academy of Technology. He joined IBM in 1962, where he has had assignments in processor development, systems architecture, and operating system design. He holds 17 patents and is an inventor on two other patent applications; all are in the area of data processing. He has received a Sixth-Level Invention Achievement Award and two Outstanding Contribution Awards. Dr. Moore received the B.E.E. degree in electrical engineering from Rensselaer Polytechnic Institute in 1961, the M.A. and Ph.D. degrees in mathematics from Syracuse University in 1969 and 1974, and the M.B.A. degree from Marist College in 1981.

Jen-Yao Chung IBM Research Division, Thomas J. Watson Research Center, P.O. Box 704, Yorktown Heights, New York 10598 (electronic mail: jychung@watson.ibm.com). Dr. Chung has been with the Thomas J. Watson Research Center, Hawthorne, NY, as a research staff member since June 1989. He currently is the manager of the data intensive computing department and is working on parallel Web server World Wide Web access to database and transaction systems, and parallel systems performance management. His research interests include Web server, database performance, parallel processing, job scheduling and load balancing in real-time systems, object-oriented programming environments, and operating system design. He has published papers in these areas and filed two patent applications. Dr. Chung received the B.S. degree in computer science and information engineering from National Taiwan University in 1982, and the M.S. and Ph.D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1986 and 1989, respectively. He has received an IBM Technical Achievement Award, a Research Division Technical Group Award, a Research Division Award, and one IEEE Outstanding Paper Award. He served as industrial chair, program committee member, and session chair in several workshops and conferences. Dr. Chung is a senior member of IEEE and a member of ACM.

Nicholas S. Bowen IBM Research Division, Thomas J. Watson Research Center, P.O. Box 704, Yorktown Heights, New York 10598 (electronic mail: bowenn@watson.ibm.com). Dr. Bowen received the B.S. degree from the University of Vermont, the M.S. degree in computer engineering from Syracuse University, and the Ph.D. in electrical and computer engineering from the University of Massachusetts at Amherst. He joined IBM at East Fishkill in 1983 and moved to the Research Center in 1986, where he is currently the department group manager of servers. He is a senior member of IEEE and a member of ACM. His research interests are operating systems, computer architecture, and fault-tolerant computing.