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Volume 34, Number 2, 1995
Scalable Parallel Computing |
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Table of contents:  HTML |
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Copyright info |
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The SP2 High-Performance Switch |
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by C. B. Stunkel, D. G. Shea, B. Abali, M. G. Atkins, C. A. Bender, D. G. Grice, P. Hochschild, D. J. Joseph, B. J. Nathanson, R. A. Swetz, R. F. Stucke, M. Tsao, and P. R. Varker |
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The heart of an IBM SP2™ system
is the HighPerformance Switch, which is a low-latency,
highbandwidth switching network that binds together RISC
System/6000®
processors. The switch incorporates a unique combination of topology
and architectural features to scale aggregate bandwidth, enhance
reliability, and simplify cabling. It is a bidirectional multistage
interconnect subsystem driven by a common oscillator, and delivers both
data and service packets over the same links. Switching elements
contain a dynamically allocated shared buffer for storing blocked
packet flits. The switch is constructed primarily from switching
elements (the Vulcan switch chip) and adapters (the SP2 communication
adapter). The SP2 communication adapter uses a variety of techniques to
improve bandwidth and offload communication tasks from the node
processor. This paper examines the switch architecture and presents an
overview of its support software.
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