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IBM Journal of Research and Development

Storage Technologies and Systems   Volume 52, Number 4/5, 2008
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Overview of candidate device technologies for storage-class memory - References

by G. W. Burr,
B. N. Kurdi,
J. C. Scott,
C. H. Lam,
K. Gopalakrishnan,
and R. S. Shenoy
References

  1. G. E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics 38, No. 8, 114–117 (1965).
  2. International Technology Roadmap for Semiconductors, ITRS 2006 Update; see http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm.
  3. K. Kim and J. Choi, “Future Outlook of NAND Flash Technology for 40nm Node and Beyond,” Proceedings of the IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, 2006, pp. 9–11.
  4. S. K. Lai, “Flash Memories: Successes and Challenges,” IBM J. Res. & Dev. 52, No. 4/5, 529–535 (2008, this issue).
  5. R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,” IEEE J. Solid-State Circ. 9, No. 5, 256–268 (1974).
  6. E. Grochowski and R. D. Halem, “Technological Impact of Magnetic Hard Disk Drives on Storage Systems,” IBM Syst. J. 42, No. 2, 338–346 (2003).
  7. D. A. Patterson, “Latency Lags Bandwidth,” Comm. ACM 47, No. 10, 71–75 (2004).
  8. R. F. Freitas and W. W. Wilcke, “Storage-Class Memory: The Next Storage System Technology,” IBM J. Res. & Dev. 52, No. 4/5, 439–447 (2008, this issue).
  9. M. Johnson, A. Al-Shamma, D. Bosch, M. Crowley, M. Farmwald, L. Fasoli, A. Ilkbahar, et al., “512-Mb PROM with a Three-Dimensional Array of Diode/Antifuse Memory Cells,” IEEE J. Solid-State Circ. 38, No. 11, 1920–1928 (2003).
  10. B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, and A. Modelli, “Multilevel Flash Cells and Their Trade-offs,” Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, 1996, pp. 169–172.
  11. K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, R. S. King, Y. Zhang, B. Kurdi, L. D. Bozano, et al., “The Micro to Nano Addressing Block (MNAB),” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2005, pp. 471–474.
  12. G. Campardo and R. Micheloni, “Special Issue on Flash Technology,” Proc. IEEE 91, No. 4, 483–488 (2003).
  13. Toshiba America Electronic Components, Inc., “NAND vs. NOR Flash Memory: Technology Overview”; see http://www.toshiba.com/taec/components/Generic/Memory_Resources/NANDvsNOR.pdf.
  14. Micron Technology, Inc., “NAND Flash 101: An Introduction to NAND Flash and How to Design It in to Your Next Product,” Technical Note No. TN-29–19; see http://download.micron.com/pdf/technotes/nand/tn2919.pdf.
  15. iSuppli Corporation; see http://isuppli.com.
  16. L. Mason, “Memory Market Outlook: DRAMs Are Nice, But All the Action Is in NAND Flash,” Proceedings of the Denali MemCon Conference, Shanghai, China, 2007; see http://www.bloobble.com/objects/presentations?itemid=454.
  17. K. Kim, “Technology for Sub-50nm DRAM and NAND Flash Manufacturing,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2005, pp. 323–326.
  18. J.-D. Lee, S.-H. Hur, and J.-D. Choi, “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Elect. Dev. Lett. 23, No. 5, 264–266 (2002).
  19. M. H. White, D. A. Adams, and J. Bu, “On the Go with SONOS,” IEEE Circ. & Dev. 16, No. 4, 22–31 (2000).
  20. W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, W. Tahui, S. Pan, C.-Y. Lu, and S. H. Gu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2001, pp. 32.6.1–32.6.4.
  21. C. W. Oh, N. Y. Kim, S. H. Kim, Y. L. Choi, S. I. Hong, H. J. Bae, J. B. Kim, et al., “4-Bit Double SONOS Memories (DSMs) Using Single-Level and Multi-Level Cell Schemes,” Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, 2006, pp. 1–4.
  22. C. H. Lee, K. I. Choi, M. K. Choi, Y. H. Song, K. C. Park, and K. Kim, “A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN Metal Gate for Multi-giga Bit Flash Memories,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 26.5.1–26.5.4.
  23. Z. L. Huo, J. K. Yang, S. H. Lim, S. J. Baik, J. Lee, J. H. Han, I.-S. Yeo, U.-I. Chung, J. T. Moon, and B.-I. Ryu, “Band Engineered Charge Trap Layer for Highly Reliable MLC Flash Memory,” Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan, 2007, pp. 138–139.
  24. R. Muralidhar, R. F. Steimle, M. Sadd, R. Rao, C. T. Swift, E. J. Prinz, J. Yater, et al., “A 6 V Embedded 90 nm Silicon Nanocrystal Nonvolatile Memory,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 26.2.1–26.2.4.
  25. B. Hwang, J. Shim, J.-H. Park, K. Lee, S. Kwon, S.-Y. Park, Y. Park, et al., “Development of Bit-Line Contact of 76 nm Pitch on NAND Flash Cell Using Reversal PR (Photo Resist) and SADP (Self-Align Double Patterning) Process,” Proceedings of the 18th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Stresa, Italy, 2007, pp. 356–358 (2007).
  26. T. Endoh, K. Kinoshita, T. Tanigami, Y. Wada, K. Sato, K. Yamada, T. Yokoyama, et al., “Novel Ultrahigh-Density Flash Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEEE Trans. Elect. Dev. 50, No. 4, 945–951 (2003).
  27. H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan, 2007, pp. 14–15.
  28. P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.-J. King, “FinFET SONOS Flash Memory for Embedded Applications,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 26.4.1–26.4.4.
  29. A. Sheikholeslami and P. G. Gulak, “A Survey of Circuit Innovations in Ferroelectric Random-access Memories,” Proc. IEEE 88, No. 5, 667–689 (2000).
  30. Y. Kato, T. Yamada, and Y. Shimada, “0.18-μm Nondestructive Readout FeRAM Using Charge Compensation Technique,” IEEE Trans. Elect. Dev. 52, No. 12, 2616–2621 (2005).
  31. K. Kim and S. Lee, “Integration of Lead Zirconium Titanate Thin Films for High Density Ferroelectric Random Access Memory,” J. Appl. Phys. 100, No. 5 051604 (2006).
  32. M. Dawber, K. M. Rabe, and J. F. Scott, “Physics of Thin-Film Ferroelectric Oxides,” Rev. Mod. Phys. 77, No. 4, 1083–1130 (2005).
  33. N. Setter, D. Damjanovic, L. Eng, G. Fox, S. Gevorgian, S. Hong, A. Kingon, et al., “Ferroelectric Thin Films: Review of Materials, Properties, and Applications,” J. Appl. Phys. 100, No. 5, 051606–051646 (2006).
  34. K. Ashikaga, K. Takaya, T. Kanehara, M. Yoshimaru, and I. Koiwa, “Reduction of Process-induced Damage and Improvement of Imprint Characteristics in SrBi2Ta2O9 Capacitors by Post Metallization Annealing,” Japan. J. Appl. Phys. 46, No. 2, 695–697 (2007).
  35. H. J. Joo, S. K. Kang, J. H. Park, H. S. Kim, J. H. Kim, J. Y. Jung, D. Y. Choi, et al., “A Novel ATE (Additional Top-Electrode) Scheme for a 1.6 V FRAM Embedded Device at 180 nm Technology,” Int. Ferro. 89, No. 1, 106–115 (2007).
  36. D. Takashima and I. Kunishima, “High-Density Chain Ferroelectric Random Access Memory (Chain FRAM),” IEEE J. Solid-State Circ. 33, No. 5, 787–792 (1998).
  37. S.-Y. Wu, “A New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductor Transistor,” IEEE Trans. Elect. Dev. 21, No. 8, 499–504 (1974).
  38. T. P. Ma and J.-P. Han, “Why Is Nonvolatile Ferroelectric Memory Field-Effect Transistor Still Elusive?”, IEEE Elect. Dev. Lett. 23, No. 7, 386–388 (2002).
  39. N. Tanabe, S. Kobayashi, T. Miwa, K. Amamuma, H. Mori, N. Inoue, T. Takeuchi, et al., “High Tolerance Operation of 1T/2C FeRAMs for the Variation of Cell Capacitors Characteristics,” Proceedings of the IEEE Symposium on VLSI Technology, Honolulu, HI, 1998, pp. 124–125.
  40. Y. K. Hong, D. J. Jung, S. K. Kang, H. S. Kim, J. Y. Jung, H. K. Koh, J. H. Park, et al., “130 nm-Technology, 0.25 μm2, 1T1C FRAM Cell for SoC (System-on-a-Chip)-friendly Applications,” Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan, 2007, pp. 230–231.
  41. K. R. Udayakumar, T. S. Moise, S. R. Summerfelt, K. Boku, K. A. Remack, J. Gertas, A. Haider, et al., “Full-Bit Functional, High-Density 8 Mbit One Transistor-One Capacitor Ferroelectric Random Access Memory Embedded within a Low-power 130 nm Logic Process,” Japan. J. Appl. Phys. 46, No. 4B, 2180–2183 (2007).
  42. S. Parkin, X. Jiang, C. Kaiser, A. Panchula, K. Roche, and M. Samant, “Magnetically Engineered Spintronic Sensors and Memory,” Proc. IEEE 91, No. 5, 661–680 (2003).
  43. M. Julliere, “Tunneling Between Ferromagnetic-Films,” Phys. Lett. A 54, No. 3, 225–226 (1975).
  44. M. Durlam, Y. Chung, M. DeHerrera, B. N. Engel, G. Grynkewich, B. Martino, B. Nguyen, J. Salter, P. Shah, and J. M. Slaughter, “MRAM Memory for Embedded and Stand Alone Systems,” Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology, Austin, TX, 2007, pp. 1–4.
  45. “Spintronics,” IBM J. Res. & Dev. 50, No. 1 (2006, entire issue).
  46. I. L. Prejbeanu, W. Kula, K. Ounadjela, R. C. Sousa, O. Redon, B. Dieny, and J.-P. Nozieres, “Thermally Assisted Switching in Exchange-Biased Storage Layer Magnetic Tunnel Junctions,” IEEE Trans. Magn. 40, No. 4, 2625–2627 (2004).
  47. J. C. Slonczewski, “Current-Driven Excitation of Magnetic Multilayers,” J. Magn. Magn. Mat. 159, No. 1/2, L1–L7 (1996).
  48. K. Miura, T. Kawahara, R. Takemura, J. Hayakawa, S. Ikeda, R. Sasaki, H. Takahashi, H. Matsuoka, and H. Ohno, “A Novel SPRAM (SPin-Transfer Torque RAM) with a Synthetic Ferrimagnetic Free Layer for Higher Immunity to Read Disturbance and Reducing Write-Current Dispersion,” Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan, pp. 234–235 (2007).
  49. S. S. P. Parkin, “Spintronic Materials and Devices: Past, Present and Future!”, Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, 2004, pp. 903–906.
  50. L. Thomas, M. Hayashi, X. Jiang, R. Moriya, C. Rettner, and S. Parkin, “Resonant Amplification of Magnetic Domain-Wall Motion by a Train of Current Pulses,” Science 315, No. 5818, 1553–1556 (2007).
  51. S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, et al., “Phase-Change Random Access Memory: A Scalable Technology,” IBM J. Res. & Dev. 52, No. 4/5, 465–479 (2008, this issue).
  52. S. Lai, “Current Status of the Phase Change Memory and its Future,” Proceedings of the IEEE International Electron Devices Meeting, Washington, D.C., 2003, pp. 10.1.1–10.1.4.
  53. A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, “Scaling Analysis of Phase-Change Memory Technology,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 29.6.1–29.6.4.
  54. Y. C. Chen, C. T. Rettner, S. Raoux, G. W. Burr, S. H. Chen, R. M. Shelby, M. Salinga, et al., “Ultra-thin Phase-change Bridge Memory Device Using GeSb,” Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, 2006, pp. 30.3.1–30.3.4.
  55. J. H. Oh, J. H. Park, Y. S. Lim, H. S. Lim, Y. T. Oh, J. S. Kim, J. M. Shin, et al., “Full Integration of Highly Manufacturable 512Mb PRAM Based on 90nm Technology,” Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, 2006, pp. 2.6.1–2.6.4.
  56. F. Pellizzer, A. Benvenuti, B. Gleixner, Y. Kim, B. Johnson, M. Magistretti, T. Marangon, A. Pirovano, R. Bez, and G. Atwood, “A 90nm Phase Change Memory Technology for Stand-alone Non-volatile Memory Applications,” Proceedings of the IEEE Symposium on VLSI Technology, Honolulu, HI, 2006, pp. 122–123.
  57. A. Chen, S. Haddad, Y.-C. Wu, T.-N. Fang, Z. Lan, S. Avanzino, S. Pangrle, et al., “Non-volatile Resistive Switching for Advanced Memory Applications,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2005, pp. 746–749.
  58. B. J. Choi, D. S. Jeong, S. K. Kim, C. Rohde, S. Choi, J. H. Oh, H. J. Kim, et al., “Resistive Switching Mechanism of TiO2 Thin Films Grown by Atomic-Layer Deposition,” J. Appl. Phys. 98, No. 3, 033715 (2005).
  59. M. Fujimoto, H. Koyama, Y. Hosoi, K. Ishihara, and S. Kobayashi, “High-Speed Resistive Switching of TiO2/TiN Nano-crystalline Thin Film,” Japan. J. Appl. Phys. 45, No. 8/11, L310–L312 (2006).
  60. Y. Hosoi, Y. Tamai, T. Ohnishi, K. Ishihara, T. Shibuya, Y. Inoue, S. Yamazaki, et al., “High Speed Unipolar Switching Resistance RAM (RRAM) Technology,” Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, 2006, pp. 30.7.1–30.7.4.
  61. D. Lee, D.-J. Seong, H. J. Choi, I. Jo, R. Dong, W. Xiang, S. Oh, et al., “Excellent Uniformity and Reproducible Resistance Switching Characteristics of Doped Binary Metal Oxides for Non-volatile Resistance Memory Applications,” Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, 2006, pp. 30.8.1–30.8.4.
  62. X. Wu, P. Zhou, J. Li, L. Y. Chen, H. B. Lin, Y. Y. Lin, and T. A. Tang, “Reproducible Unipolar Resistance Switching in Stoichiometric ZrO2 Films,“, Appl. Phys. Lett. 90, No. 18, 183507–183510 (2007).
  63. H.-Y. Lee, P.-S. Chen, C.-C. Wang, S. Maikap, P.-J. Tzeng, C.-H. Lin, L.-S. Lee, and M.-J. Tsai, “Low-Power Switching of Nonvolatile Resistive Memory Using Hafnium Oxide,” Japan. J. Appl. Phys. 46, No. 4B, 2175–2179 (2007).
  64. C. H. Ho, E. K. Lai, M. D. Lee, C. L. Pan, Y. D. Yao, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A Highly Reliable Self-aligned Graded Oxide WOx Resistance Memory: Conduction Mechanisms and Reliability,” Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan, 2007, pp. 228–229.
  65. J. F. Gibbons and W. E. Beadle, “Switching Properties of Thin NiO Films,” Solid State Elect. 7, No. 11, 785–790 (1964).
  66. I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park, et al., “Highly Scalable Nonvolatile Resistive Memory Using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses,” Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, 2004, pp. 587–590.
  67. K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, Y. Yamazaki, T. Fukano, S. Yagaki, M. Aoki, and Y. Sugiyama, “Reduction of Reset Current in NiO-ReRAM Brought About by Ideal Current Limiter,” Proceedings of the 22nd IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, 2007, pp. 66–67.
  68. A. Beck, J. G. Bednorz, C. Gerber, C. Rossel, and D. Widmer, “Reproducible Switching Effect in Thin Oxide Films for Memory Applications,” Appl. Phys. Lett. 77, No. 1, 139–141 (2000).
  69. S. F. Karg, G. I. Meijer, J. G. Bednorz, C. T. Rettner, A. G. Schrott, E. A. Joseph, C. H. Lam, et al., “Transition-Metal-Oxide-Based Resistance-Change Memories,” IBM J. Res. & Dev. 52, No. 4/5, 481–492 (2008, this issue).
  70. M. N. Kozicki, M. Park, and M. Mitkova, “Nanoscale Memory Elements Based on Solid-state Electrolytes,” IEEE Trans. Nano. 4, No. 3, 331–338 (2005).
  71. M. N. Kozicki, M. Balakrishnan, C. Gopalan, C. Ratnakumar, and M. Mitkova, “Programmable Metallization Cell Memory Based on Ag-Ge-S and Cu-Ge-S Solid Electrolytes,” Proceedings of the 20th IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, 2005, pp. 83–89.
  72. M. Kund, G. Beitel, C.-U. Pinnow, T. Röhr, J. Schumann, R. Symanczyk, K.-D. Ufert, and G. Müller, “Conductive Bridging RAM (CBRAM): An Emerging Non-volatile Memory Technology Scalable to Sub 20nm,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, 2005, pp. 754–757 (2005).
  73. P. Schrögmeier, M. Angerbauer, S. Dietrich, M. Ivanov, H. Hönigschmid, C. Liaw, M. Markert, et al., “Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2 Multilevel CBRAM,” Proceedings of the IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 186–187 (2007).
  74. C. J. Kim, S. G. Yoon, K. J. Choi, S. O. Ryu, S. M. Yoon, N. Y. Lee, and B. G. Yu, “Characterization of Silver-saturated Ge-Te Chalcogenide Thin Films for Nonvolatile Random Access Memory,” J. Vac. Sci. & Tech. B 24, No. 2, 721–724 (2006).
  75. D. Lee, D.-J. Seong, I. Jo, F. Xiang, R. Dong, S. Oh, and H. Hwang, “Resistance Switching of Copper Doped MoOx Films for Nonvolatile Memory Applications,” Appl. Phys. Lett. 90, No. 12, 122104 (2007).
  76. L. V. Gregor, “Polymer Dielectric Films,” IBM J. Res. & Dev. 12, No. 2, 140–162 (1968).
  77. J. C. Scott and L. D. Bozano, “Nonvolatile Memory Elements Based on Organic Materials,” Adv. Mater. 19, 1452–1463 (2007).
  78. Q. Ling, Y. Song, S. J. Ding, C. Zhu, D. S. H. Chan, D.-L. Kwong, E.-T. Kang, and K.-G. Neoh, “Non-volatile Polymer Memory Device Based on a Novel Copolymer of N-vinylcarbazole and Eu-Complexed Vinylbenzoate,” Adv. Mater. 17, No. 4, 455–459 (2005).
  79. B. Pradhan, S. K. Batabyal, and A. J. Pal, “Electrical Bistability and Memory Phenomenon in Carbon Nanotube-conjugated Polymer Matrixes,” J. Phys. Chem. B 110, No. 16, 8274–8277 (2006).
  80. R. S. Potember, T. O. Poehler, and D. O. Cowan, “Electrical Switching and Memory Phenomena in Cu-TCNQ Thin Films,” Appl. Phys. Lett. 34, No. 6, 405–407 (1979).
  81. C.-W. Chu, J. Ouyang, J.-H. Tseng, and Y. Yang, “Organic Donor-Acceptor System Exhibiting Electrical Bistability for Use in Memory Devices,” Adv. Mater. 17, 1440–1443 (2005).
  82. F. Verbakel, S. C. J. Meskers, and R. A. J. Janssen, “Electronic Memory Effects in a Sexithiophene-poly(ethylene oxide) Block Copolymer Doped with NaCl Combined Diode and Resistive Switching Behavior,” Chem. Mater. 18, No. 11, 2707–2712 (2006).
  83. L. D. Bozano, B. W. Kean, V. R. Deline, J. R. Salem, and J. C. Scott, “Mechanism for Bistability in Organic Memory Elements,” Appl. Phys. Lett. 84, No. 4, 607–609 (2004).
  84. L. D. Bozano, B. W. Kean, M. Beinhoff, K. R. Carter, P. M. Rice, and J. C. Scott, “Organic Materials and Thin-Film Structures for Cross-point Memory Cells Based on Trapping in Metallic Nanoparticles,” Adv. Func. Mater. 15, No. 12, 1933–1939 (2005).
  85. G. Dearnaley, D. V. Morgan, and A. M. Stoneham, “A Model for Filament Growth and Switching in Amorphous Oxide Films,” J. Non-Cryst. Solids 4, 593–612 (1970).
  86. H. Pagnia and N. Sotnik, “Bistable Switching in Electroformed Metal-Insulator-Metal Devices,” Phys. Stat. Sol. A 108, No. 1, 11–65 (1988).
  87. A. Bandyopadhyay and A. J. Pal, “Key to Design Functional Organic Molecules for Binary Operation with Large Conductance Switching,” Chem. Phys. Lett. 371, No. 1/2, 86–90 (2003).
  88. D. M. Taylor and C. A. Mills, “Memory Effect in the Current–Voltage Characteristic of a Low-Band Gap Conjugated Polymer,” J. Appl. Phys. 90, No. 1, 306–309 (2001).
  89. J. G. Simmons and R. R. Verderber, “New Conduction and Reversible Memory Phenomena in Thin Insulating Films,” Proc. Royal Soc. London A 301, No. 1464, 77–102 (1967).
  90. Y. Yang, J. Ouyang, L. Ma, R. J.-H. Tseng, and C.-W. Chu, “Electrical Switching and Bistability in Organic/Polymeric Thin Films and Memory Devices,” Adv. Funct. Mater. 16, 1001–1014 (2006).
  91. W. Tang, H. Z. Shi, G. Xu, B. S. Ong, Z. D. Popovic, J. C. Deng, J. Zhao, and G. H. Rao, “Memory Effect and Negative Differential Resistance by Electrode-Induced Two-dimensional Single-Electron Tunneling in Molecular and Organic Electronic Devices,” Adv. Mater. 17, No. 19, 2307–2311 (2005).
  92. M. Shin, S. Lee, K. W. Park, and E.-H. Lee, “Secondary Coulomb Blockade Gap in a Four-Island Tunnel-Junction Array,” Phys. Rev. 59, No. 4, 3160–3167 (1999).


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