IBM®
Skip to main content
    Country/region [change]    Terms of use
 
 
 
    Home    Products    Services & solutions    Support & downloads    My account    

IBM Journal of Research and Development
Soft Errors in Circuits and Systems   Volume 52, Number 3, 2008
Table of contents: HTMLPDF This article: HTMLPDF   Copyright info

Soft-error resilience of the IBM POWER6 processor - References

 by P. N. Sanda,
J. W. Kellington,
P. Kudva,
R. Kalla,
R. B. McBeth,
J. Ackaret,
R. Lockwood,
J. Schumann,
and C. R. Jones
References

  1. SELSE 2, The Second Workshop on System Effects of Logic Soft Errors, University of Illinois, Urbana–Champaign, IL, April 11–12, 2006; see http://selse2.selse.org.
  2. N. J. Wang, J. Quek, T. M. Rafacz, and S. J. Patel, “Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline,” Proceedings of the 2004 International Conference on Dependable Systems and Networks, Florence, Italy, 2004, pp. 61–70.
  3. A. Biswas, P. Razvan, R. Cheveresan, J. Emer, S. S. Mukherjee, and R. Rangan, “Computing Architectural Vulnerability Factors for Address-Based Structures,” Proceedings of the 32nd International Symposium on Computer Architecture, Madison, WI, 2005, pp. 532–543.
  4. X. Li, S. V. Adve, P. Bose, and J. A. Rivers, “SoftArch: An Architecture-Level Tool for Modeling and Analyzing Soft Errors,” Proceedings of the International Conference on Dependable Systems and Networks, Yokohama, Japan, 2005, pp. 496–505.
  5. H. T. Nguyen, Y. Yagil, N. Seifert, and M. Reitsma, “Chip-Level Soft Error Estimation Model,” IEEE Trans. Dev. Mat. Rel. 5, No. 3, 365–381 (2005).
  6. S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin, “A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor,” Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, San Diego, CA, 2003, pp. 29–40.
  7. C. Constantinescu, “Neutron SER Characterization of Microprocessors,” Proceedings of the International Conference on Dependable Systems and Networks, Yokohama, Japan, 2005, pp. 754–759.
  8. C. Bender, P. N. Sanda, P. Kudva, R. Mata, V. Pokala, R. Haraden, and M. Schallhorn, “Soft-Error Resilience of the IBM POWER6 Processor Input/Output Subsystem,” IBM J. Res. & Dev. 52, No. 3, 285–292 (2008, this issue).
  9. J. L. Peterson, P. J. Bohrer, L. Chen, E. N. Elnozahy, A. Gheith, R. H. Jewell, M. D. Kistler, et al., “Application of Full-System Simulation in Exploratory System Design and Development,” IBM J. Res. & Dev. 50, No. 2/3, 321–332 (2006).
  10. H. Q. Le, W. J. Starke, J. S. Fields, F. P. O'Connell, D. Q. Nguyen, B. J. Ronchetti, W. M. Sauer, E. M. Schwarz, and M. T. Vaden, ‘‘IBM POWER6 Microarchitecture,” IBM J. Res. & Dev. 51, No. 6, 639–661 (2007).
  11. J. Fredrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, et al., “Design of the POWER6 Microprocessor,” Proceedings of the IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, CA, 2007, pp. 96–97.
  12. J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, “POWER4 System Microarchitecture,” IBM J. Res. & Dev. 46, No. 1, 5–25 (2002).
  13. E. W. Casio, J. M. Sisterson, J. B. Flanz, and M. S. Wagner, “The Proton Irradiation Program at the Northeast Proton Therapy Center,” Proceedings of the IEEE Radiation Effects Data Workshop, Monterey, CA, 2003, pp. 141–144.
  14. J. Blome, S. Mahlke, D. Bradley, and K. Flautner, “A Microarchitectural Analysis of Soft Error Propagation in a Production-Level Embedded Microprocessor,” Proceedings of the 1st Workshop on Architectural Reliability, 38th International Symposium on Microarchitecture, Barcelona, Spain, 2005; see http://www.cs.binghamton.edu/~oguz/war2005/papers/war_final3.pdf.
  15. D. C. Bossen, A. Kitamorn, K. F. Reick, and M. S. Floyd, “Fault-Tolerant Design of the IBM pSeries 690 System Using POWER4 Processor Technology,” IBM J. Res. & Dev. 46, No. 1, 77–86 (2002).
  16. J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, et al., “Functional Verification of the POWER4 Microprocessor and POWER4 Multiprocessor Systems,” IBM J. Res. & Dev. 46, No. 1, 53–76 (2002).
  17. M. E. Wazlowski, N. R. Adiga, D. K. Beece, R. Bellofatto, M. A. Blumrich, D. Chen, M. B. Dombrowa, et al., “Verification Strategy for the Blue Gene/L Chip,” IBM J. Res. & Dev. 49, No. 2/3, 303–318 (2005).
  18. G. G. Brown and H. C. Rutemiller, “Evaluation of Pr {x ≥ y} When Both X and Y are from Three-Parameter Weibull Distributions,” IEEE Trans. Rel. R-22, No. 2, 78–82 (1973).


    About IBM    Privacy    Contact