Pia N. Sanda IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (sandaus.ibm.com). Dr. Sanda is a Senior Technical Staff Member in the Technology Development. She works on soft-error reliability to ensure the dependability of server systems. She is known for her pioneering work to develop picosecond imaging circuit analysis (PICA), which measures and creates a visualization of the actual switching behavior of high-performance microprocessors to verify timing. She has also invented algorithms for phase-shift mask generation, which are used in integrated circuit autogeneration tools. She received a B.S. degree in engineering physics and a Ph.D. degree in physics, both from Cornell University. She is a member of the IBM Academy of Technology.

Jeffrey W. Kellington IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (jwkellinus.ibm.com). Mr. Kellington is a Staff Functional Verification Engineer for IBM System p* development. His current responsibilities include running Linux and assembly-based functional exercisers and benchmark programs on development hardware and verification models. His past experience with the POWER5 and POWER6 processors and their pre- and post-silicon verification has contributed to extensive knowledge of the POWER* microprocessor and RAS microarchitecture. He received his B.S. degree in computer engineering from the University of Illinois.

Prabhakar Kudva IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (kudvaus.ibm.com). Dr. Kudva received a Ph.D. degree in computer science from the University of Utah in 1995. He has been a Research Staff Member at the IBM T. J. Watson Research Center since then. He works in the areas of design automation, processor architecture, circuit design, and methodology for high-end microprocessors and application-specific integrated circuits (ASICs). He holds several patents, has published numerous papers, and has served on various conference technical program committees in these areas. He has received several awards including the Outstanding Technical Accomplishment and Research Division Awards from IBM as well as an IEEE/ACM William J. McCalla ICCAD Best Paper Award. He is an Adjunct Professor at Columbia University.

Ronald Kalla IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (rkallaus.ibm.com). Mr. Kalla is a Distinguished Engineer in the IBM server group processor development. His research interests include computer microarchitecture and post-silicon processor verification. He is an IBM master inventor and holds several patents in processor architecture. He has worked in processor development for more than 20 years on multiple instruction set architectures. He holds a B.S.E.E. degree from the University of Minnesota.

Ryan B. McBeth IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (rmcbethus.ibm.com). Mr. McBeth received a B.S. degree in electrical engineering from the University of Texas at Austin in 2003. He joined IBM in the Central Electronic Complex Bring-up and Integration Department. He began work on the POWER6 processor simulation with the virtual bring-up team. He next followed the POWER6 processor into the laboratory where he participated in developing and using an automated testing environment to run thousands of hours of test code, primarily targeting the POWER6 processor core. For the past year, he has worked as the CEC bring-up and integration leader on the POWER6 processor-based blade server.

Jerry Ackaret IBM Systems and Technology Group, 15400 S.W. Koll Parkway, Beaverston, Oregon 97006 (jatus.ibm.com). Mr. Ackaret is the Senior Hardware Reliability Engineer for IBM System x* servers. He is responsible for the reliability activities for System x products, including projections and statistical analysis of field and test data. He is the creator of the hardware reliability methodology for System x, which defines the reliability parameters, processes, and measurement activities. He holds three patents. He was the International Disk Drive Equipment and Materials Association Disk Drive Reliability Committee co-chair during the creation and maintenance of the standards for the disk drive industry concerning how to specify the test, report, and reliability values. He received his B.S.E.E. degree from the University of Idaho.

Ryan Lockwood IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 (rlockwous.ibm.com). Mr. Lockwood, while at the University of Vermont, participated in a co-op program with the IBM PowerPC* Product Engineering group. His interest in microprocessors led him to start a career in diagnosing and characterizing defects within the processors. He is currently serving as a Staff Product Engineer for the PowerPC Technology Development team. His responsibilities include the development and maintenance of numerous tools used to automate and expedite the delivery of critical defect information to the Failure Analysis team.

John Schumann IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (johnschuus.ibm.com). Mr. Schumann joined IBM after receiving a B.S. degree in electrical engineering in 1996 from the University of Texas at Austin. He initially worked on POWER3* processor verification. He has continued in the verification field with varying roles for POWER4*, PowerPC 970, and POWER6 microprocessors.

Christopher R. Jones IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (crjonesus.ibm.com). After receiving a B.S. degree in computer engineering in 1999 from Texas A&M University, Mr. Jones started work for the Processor Pre-silicon Chip Hardware Logic Verification department at IBM. He participated in chip- and system-level RAS processor and ASIC logic testing for the POWER5, POWER6, and z6 processor development. He is a member of the Exercisers on Accelerators Verification group for POWER7* processor development.

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