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IBM Journal of Research and Development

Soft Errors in Circuits and Systems   Volume 52, Number 3, 2008
Table of contents: HTMLPDF This article: HTMLPDF   Copyright info

Phaser: Phased methodology for modeling the system-level effects of soft errors - Author Bios

by J. A. Rivers,
P. Bose,
P. Kudva,
J.-D. Wellman,
P. N. Sanda,
E. H. Cannon,
and L. C. Alves
Biographical sketches of authors

Jude A. Rivers IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (jarivers@us.ibm.com). Dr. Rivers is a Research Staff Member in the Reliability- and Power-Aware Microarchitectures department. He received a Ph.D. degree in computer science and engineering from the University of Michigan at Ann Arbor in 1998. He then joined IBM Research where he has focused on a wide range of high-performance computer architecture issues and innovations, including hypercaching, efficient instruction and data supply for server systems, power-aware microarchitecture design and analysis, embedded systems, and reliability-aware design and analysis. He has authored several refereed publications, is the author or coauthor of six issued patents, and has more than 20 pending patent applications. He has received several IBM Invention Plateau Awards and a Research Technical Group Award. Dr. Rivers is a member of the IEEE.

Pradip Bose IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (pbose@us.ibm.com). Dr. Bose received a Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana–Champaign in 1983. Since then he has been with IBM Research where he currently manages the Reliability- and Power-Aware Microarchitectures department. He has been involved in the design and presilicon modeling of virtually all IBM POWER microprocessor series. His current research interests are in high-performance computers, power- and reliability-aware microprocessor architectures, presilicon modeling and validation, compilers, and design automation. He is the author or coauthor of more than 70 refereed publications, including several book chapters. He has received several IBM Invention Plateau Awards, a Research Accomplishment Award, and an Outstanding Innovation Award from IBM. He served as Editor-in-Chief of IEEE Micro from 2003 to 2006. Dr. Bose is an IEEE Fellow.

Prabhakar Kudva IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (kudva@us.ibm.com). Dr. Kudva received a Ph.D. degree in computer science from the University of Utah in 1995. He has been a Research Staff Member at the IBM Thomas J. Watson Research Center since then. He works in the areas of design automation, processor architecture, high-end microprocessor circuit design and methodology, and ASICs. He holds several patents, has published numerous papers, and has served on various conference technical program committees in these areas. He has received several awards including the Outstanding Technical Accomplishment and Research Division Awards from IBM as well as an IEEE/ACM William J. McCalla ICCAD Best Paper Award. Dr. Kudva is an Adjunct Professor at Columbia University.

John-David Wellman IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (wellman@us.ibm.com). Dr. Wellman is a Research Staff Member in the Systems Technology and Microarchitecture department. He received a Ph.D. degree in computer science and engineering from the University of Michigan in 1996, at which time he joined IBM Research. He has focused on the modeling and analysis of computer performance and the simulation and verification of digital logic to improve aspects of processor performance. He has participated in the design and implementation of the IBM POWER4* microprocessor, and was a principal member of the IBM Research team that worked with Sony and Toshiba to develop the concept design for what is now the Cell Broadband Engine**. Dr. Wellman is an author or coauthor of more than 20 patents and several papers.

Pia N. Sanda IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (sanda@us.ibm.com). Dr. Sanda received a B.S. degree in engineering physics and a Ph.D. degree in physics, both from Cornell University. She is a Senior Technical Staff Member for server development, working on the soft-error reliability of server systems. She is known for her pioneering work in the development of PICA (picosecond imaging circuit analysis) to measure and visualize the actual switching behavior of high-performance microprocessors to verify timing. She also invented algorithms for phase-shift mask generation which are used in integrated circuit autogeneration tools. Dr. Sanda is a member of the IBM Academy of Technology.

Ethan H. Cannon IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 (cannon1@us.ibm.com). Dr. Cannon received a B.S. degree in engineering physics from the University of California, Berkeley, in 1994, and M.S. and Ph.D. degrees in physics from the University of Illinois at Urbana–Champaign, in 1995 and 1999, respectively. After postdoctoral studies at the University of Notre Dame, he joined IBM. Dr. Cannon is currently a reliability engineer focusing on soft-error simulations and measurements.

Luiz C. Alves IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (alves@us.ibm.com). Mr. Alves is a Senior Technical Staff Member working in the System z* Reliability, Availability and Serviceability group. He graduated from New York University in 1975 with a B.S. degree in electrical engineering and received an M.S. degree in electrical engineering in 1977 from the Polytechnic Institute of New York. He joined IBM in 1977 working in the advanced system manufacturing engineering organization, where he held various technical and managerial positions. In 1985 he was named field quality assurance manager for the IBM 3090* system, and in 1987 he became the RAS manager for the 9021 processor families. Mr. Alves is currently responsible for defining the RAS requirements for future System z products.

*Trademark, service mark, or registered trademark of International Business Machines Corporation in the United States, other countries, or both.
**Trademark, service mark, or registered trademark of Standard Performance Evaluation Corporation, Cadence Design Systems, Inc., or Sony Computer Entertainment, Inc., in the United States, other countries, or both.


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