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IBM Journal of Research and Development
Soft Errors in Circuits and Systems   Volume 52, Number 3, 2008
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Alpha-particle-induced upsets in advanced CMOS circuits and technology - References

 by D. F. Heidel,
K. P. Rodbell,
E. H. Cannon,
C. Cabral, Jr.,
M. S. Gordon,
P. Oldiges,
and H. H. K. Tang
References

  1. D. G. Mavis and P. H. Eaton, “SEU and SET Modeling and Mitigation in Deep Submicron Technologies,” 2007 Proceedings of the 45th Annual IEEE International Reliability Physics Symposium, 2007, pp. 293–305.
  2. G. Gasiot, D. Giot, and P. Roche, “Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm SRAMs and Its Dependence on Well Engineering,” IEEE Trans. Nucl. Sci. 54, No. 6, 2468–2473 (2007).
  3. P. Roche and G. Gasiot, “Impacts of Front-End and Middle-End Process Modifications on Terrestrial Soft Error Rate,” IEEE Trans. Device Mater. Reliability 5, No. 3, 382–396 (2005).
  4. D. F. Heidel, K. P. Rodbell, P. Oldiges, M. S. Gordon, H. H. K. Tang, E. H. Cannon, and C. Plettner, “Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells,” IEEE Trans. Nucl. Sci. 53, No. 6, 3512–3517 (2006).
  5. A. KleinOsowski, P. Oldiges, R. Q. Williams, and P. M. Solomon, “Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices”, IEEE Trans. Nucl. Sci. 53, No. 6, 3321–3328 (2006).
  6. A. KleinOsowski, E. H. Cannon, P. Oldiges, and L. Wissel, “Circuit Design and Modeling for Soft Errors,” IBM J. Res. & Dev. 52, No. 3, 255–263 (2008, this issue).
  7. P. Oldiges, R. Dennard, D. Heidel, B. Klaasen, F. Assaderaghi, and M. Ieong, “Theoretical Determination of the Temporal and Spatial Structure of alpha-Particle Induced Electron-Hole Pair Generation in Silicon,” IEEE Trans. Nucl. Sci. 47, No. 6, 2575–2579 (2000).
  8. E. M. Buturla, P. E. Cottrell, B. M. Grossman, and K. A. Salsburg, “Finite-Element Analysis of Semiconductor Devices: The FIELDAY Program,” IBM J. Res. & Dev. 25, No. 4, 218–231 (1981).
  9. H. H. K. Tang and E. H. Cannon, “SEMM-2: A Modeling System for Single Event Upset Analysis,” IEEE Trans. Nucl. Sci. 51, No. 6, 3342–3348 (2004).
  10. P. C. Murley and G. R. Srinivasan, “Soft-Error Monte Carlo Modeling Program, SEMM,” IBM J. Res. & Dev. 40, No. 1, 109–118 (1996).
  11. P. N. Sanda, J. W. Kellington, P. Kudva, R. Kalla, R. B. McBeth, J. Ackaret, R. Lockwood, J. Schumann, and C. R. Jones, “Soft-Error Resilience of the IBM POWER6 Processor,” IBM J. Res. & Dev. 52, No. 3, 275–284 (2008, this issue).
  12. C. Cabral, Jr., K. P. Rodbell, and M. S. Gordon, “Alpha Particle Mitigation Strategies to Reduce Chip Soft Error Upsets,” J. Applied Phys. 101, No. 1, 014902-1–014902-6 (2007).
  13. K. P. Rodbell, D. F. Heidel, H. H. K. Tang, M. S. Gordon, P. Oldiges, and C. Murray, “Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node Silicon-on-Insulator Latches and Memory Cells,” IEEE Trans. Nucl. Sci. 54, No. 6, 2474–2479 (2007).


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