Carl Bender IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (cabenderus.ibm.com). Mr. Bender is a Senior Technical Staff Member in the I/O ASICs Development team. He joined IBM in 1988 after graduating from Clarkson University with a B.S. degree in electrical engineering. He has worked on various development projects including high-performance networking hardware and software and I/O ASIC design, and he was responsible for the hardware and firmware integration and test for the POWER6 processor I/O subsystem. He is currently responsible for the development of the next-generation storage interface for IBM System z* products.

Pia N. Sanda IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (sandaus.ibm.com). Dr. Sanda is a Senior Technical Staff Member of the Poughkeepsie-based Technology Development team. She currently works on soft-error reliability to ensure the dependability of server systems. She is known for her pioneering work to develop picosecond imaging circuit analysis (PICA), which measures and creates a visualization of the switching behavior of high-performance microprocessors to verify timing. She has also invented algorithms for phase-shift mask generation, which are used in integrated circuit autogeneration tools. She received a B.S. degree in engineering physics and a Ph.D. degree in physics, both from Cornell University. She is a member of the IBM Academy of Technology.

Prabhakar Kudva IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (kudvaus.ibm.com). Dr. Kudva received a Ph.D. degree in computer science from the University of Utah in 1995. He has been a Research Staff Member at the IBM T. J. Watson Research Center since then. He works in the areas of design automation, processor architecture, and circuit design and methodology for high-end microprocessors and ASICs. He holds several patents, has published numerous papers, and has served on various conference technical program committees in these areas. He has received several awards including the Outstanding Technical Accomplishment and Research Division Awards from IBM, and the IEEE/ACM William J. McCalla ICCAD Best Paper Award. He is an Adjunct Professor at Columbia University.

Ricardo Mata IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (ricmataus.ibm.com). Mr. Mata is responsible for the bring-up and verification of the IBM POWER processor-based system I/O subsystems and has been the test leader for proton and neutron beam irradiation studies of the I/O hub chip. He received his B.S. degree in electrical engineering from the University of Texas–Pan American.

Vikas Pokala IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (vpokalaus.ibm.com). Mr. Pokala joined the Hardware Verification Department at IBM in 2005 after receiving an M.S. degree in electrical engineering from the University of Southern California. He started working on the IBM POWER5+* processor characterization and shipped product quality level for high-end servers. He is currently responsible for characterization of the POWER6 high-end server and EnergyScale* functions across all POWER6 processor-based servers.

Ryan Haraden IBM Systems and Technology Group, 3605 Highway 52 North, Rochester, Minnesota 55901 (haradenus.ibm.com). Mr. Haraden started his career at IBM in 1995 in system simulation on IBM POWER4* and POWER5* chipsets. He received an M.S. degree in computer engineering in 2000 from the National Technological University. He then moved to an ASIC hardware design group. He has since worked on a variety of I/O chips spanning many I/O protocols: RIO, RIOG, GX+, InfiniBand**, PCI, PCI-X, PCIe, and currently fully buffered DIMM2. He holds several patents in I/O hardware design.

Matthew Schallhorn IBM Systems and Technology Group, 3605 Highway 52 North, Rochester, Minnesota 55901 (schallh1us.ibm.com). Mr. Schallhorn received a B.S. degree in electrical engineering in 2001 from Michigan State University. He then began working in ASIC logic design of I/O hubs for the POWER4, POWER5, and POWER6 families of servers. He is currently a design-for-test engineer in the IBM Global Engineering Solutions organization.

*Trademark, service mark, or registered trademark of International Business Machines Corporation in the United States, other countries, or both.
**Trademark, service mark, or registered trademark of PCI-SIG Corporation, Linus Torvalds, or InfiniBand Trade Association in the United States, other countries, or both.