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IBM Journal of Research and Development
IBM POWER6 Microprocessor Technology   Volume 51, Number 6, 2007
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IBM POWER6 microarchitecture - References

 by H. Q. Le,
W. J. Starke,
J. S. Fields,
F. P. O'Connell,
D. Q. Nguyen,
B. J. Ronchetti,
W. M. Sauer,
E. M. Schwarz,
and M. T. Vaden
References

  1. B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Joyner, “POWER5 System Microarchitecture,” IBM J. Res. & Dev. 49, No. 4/5, 505–521 (2005).
  2. J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, “POWER4 System Microarchitecture,” IBM J. Res. & Dev. 46, No. 1, 5–25 (2002).
  3. W. J. Armstrong, R. L. Arndt, T. R. Marchini, N. Nayar, and W. M. Sauer, “IBM POWER6 Partition Mobility: Moving Virtual Servers Seamlessly Between Physical Systems,” IBM J. Res. & Dev. 51, No. 6, 757–762 (2007, this issue).
  4. T. N. Buti, R. G. McDonald, Z. Khwaja, A. Ambekar, H. Q. Le, W. E. Burky, and B. Williams, “Organization and Implementation of the Register-renaming Mapper for Out-of-order IBM POWER4 Processors,” IBM J. Res. & Dev. 49, No. 1, 167–188 (2005).
  5. D. Lenoski, J. Laudon, K. Gharachorloo, W.-D. Weber, A. Gupta, J. Hennessy, M. Horowitz, and M. S. Lam, “The Stanford Dash Multiprocessor,” Computer 25, No. 3, 63–79 (1992).
  6. B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y.-H. Chan, D. Webber, M. Vaden, and A. Goyal, “4GHz+ Low-Latency Fixed-Point and Binary Floating-Point Execution Units for the POWER6 Processor,” Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, February 2006, pp. 1712–1734.
  7. R. Kalla, B. Sinharoy, and J. M. Tendler, “IBM POWER5 Chip: A Dual-Core Multithreaded Processor,” IEEE Micro 24, 40–47 (2004).
  8. E. M. Schwarz, M. Schmookler, and S. D. Trong, “FPU Implementations with Denormalized Numbers,” IEEE Transactions on Computers 54, No. 7, 825–836 (2005).
  9. X. Y. Yu, Y.-H. Chan, M. Kelly, E. Schwarz, B. Curran, and B. Fleischer, “A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor,” Proceedings of the 32nd European Solid-State Circuits Conference, Montreux, Switzerland, September 2006; see http://www.ece.ucdavis.edu/~yanzi/esscirc06_submit.pdf.
  10. S. D. Trong, M. Schmookler, E. M. Schwarz, and M. Kroener, “P6 Binary Floating-Point Unit,” Proceedings of the 18th IEEE Symposium on Computer Arithmetic, Montpellier, France, 2007, pp. 77–86.
  11. E. M. Schwarz, “Binary Floating-Point Unit Design: The Fused Multiply-add Dataflow,” High-Performance Energy-Efficient Microprocessor Design, V. G. Oklobdzija and R. K. Krishnamurthy, Eds., Springer, Dordrecht, The Netherlands, 2006, pp. 189–208.
  12. L. Eisen, J. W. Ward III, H.-W. Tast, N. Mäding, J. Leenstra, S. M. Mueller, C. Jacobi, J. Preiss, E. M. Schwarz, and S. R. Carlough, “IBM POWER6 Accelerators: VMX and DFU,” IBM J. Res. & Dev. 51, No. 6, 663–683 (2007, this issue).
  13. M. J. Mack, W. M. Sauer, S. B. Swaney, and B. G. Mealey, “IBM POWER6 Reliability,” IBM J. Res. & Dev. 51, No. 6, 763–774 (2007, this issue).
  14. J. W. Kellington, R. McBeth, P. Sanda, and R. N. Kalla, “IBM® POWER6™ Processor Soft Error Tolerance Analysis Using Proton Irradiation,” Proceedings of the IEEE Workshop on Silicon Errors in Logic—Systems Effects (SELSE) Conference, Austin, TX, April 2007; see http://www.selse.org/Papers/28_Kellington_P.pdf.
  15. D. W. Plass and Y. H. Chan, “IBM POWER6 SRAM Arrays,” IBM J. Res. & Dev. 51, No. 6, 747–756 (2007, this issue).
  16. F. P. O'Connell and S. W. White, “POWER3: The Next Generation of PowerPC Processors,” IBM J. Res. & Dev. 44, No. 6, 873–884 (2000).


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