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IBM Journal of Research and Development
IBM System z9   Volume 51, Number 1/2, 2007
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High-speed interconnect and packaging design of the IBM System z9 processor cage - References

 by H. Harrer,
D. M. Dreps,
T.-M. Winkel,
W. Scholz,
B. G. Truong,
A. Huber,
T. Zhou,
K. L. Christian,
and G. F. Goth
References

  1. H. Harrer, H. Pross, T.-M. Winkel, W. D. Becker, H. I. Stoller, M. Yamamoto, S. Abe, B. J. Chamberlin, and G. A. Katopis, “First- and Second-Level Packaging for the IBM eServer* z900,” IBM J. Res. & Dev. 46, No. 4/5, 397–420 (2002).
  2. T.-M. Winkel, W. D. Becker, H. Harrer, H. Pross, D. Kaller, B. Garben, B. J. Chamberlin, and S. A. Kuppinger, “First- and Second-Level Packaging of the z990 Processor Cage,” IBM J. Res. & Dev. 48, No. 3/4, 379–394 (2004).
  3. G. A. Katopis, W. D. Becker, and H. Harrer, “T-Rex, a Blade Packaging Architecture for Mainframe Servers,” IEEE Trans. Adv. Pkg. 28, No. 1, 24–31 (2005).
  4. E. Cordero, D. Dreps, F. Ferraiolo, M. Floyd, K. Gower, and B. McCredie, “A Synchronous Wave Pipeline Interface for POWER4,” presented at the IEEE Computer Society HOT CHIPS Workshop, Stanford University, CA, August 15–17, 1999.
  5. J. C. Parrilla, F. E. Bosco, J. S. Corbin, J. J. Loparco, P. Singh, and J. G. Torok, “Packaging the IBM eServer z990 Central Electronic Complex,” IBM J. Res. & Dev. 48, No. 3/4, 395–407 (2004).
  6. P. A. Coico, G. Messina, S. Ostrander, J. Zitz, and W. Zou, “Internal Thermal Management of IBM p-Server Large Format Multichip Modules Utilizing Small Gap Technology,” Proceedings of the ASME/PACIFIC Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS and Electronic Systems, 2005, Paper 73422, six pages.
  7. A. Huber, T. Zhou, W. D. Becker, R. Weekly, and E. Klink, “Power Distribution Analysis for IBM eServer System Integration Optimization,” Proceedings of the Conference on Electrical Performance of Electronic Packaging (EPEP), Portland, OR, 2004, pp. 189–192.
  8. IBM Electromagnetic Field Solver Suite of Tools, May 2006; see www.alphaworks.ibm.com/tech/eip.
  9. D. M. Berger, J. Y. Chen, F. D. Ferraiolo, J. A. Magee, and G. A. Van Huben, “High-Speed Source-Synchronous Interface for the IBM System z9 Processor,” IBM J. Res. & Dev. 51, No. 1/2, 53–64 (2007, this issue).


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