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Advanced Silicon Technology
Volume 50, Number 4/5, 2006
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Three-dimensional integrated circuits - References
by A. W.
Topol
,
D. C.
La Tulipe, Jr.
,
L.
Shi
,
D. J.
Frank
,
K.
Bernstein
,
S. E.
Steen
,
A.
Kumar
,
G. U.
Singco
,
A. M.
Young
,
K. W.
Guarini
,
and M.
Ieong
References
H.-S. P. Wong,
“Beyond the Conventional Transistor,”
IBM J. Res. & Dev
.
46
, No. 2/3, 133 (2002).
V. Agarwal, M. S. Hrishikash, S. W. Keckler, and D. Burger, “Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures,”
Comput. Arch. News
28
, 248 (2000).
R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,”
IEEE J. Solid-State Circuits
SC-9
, 256 (1974).
G. G. Shahidi,
“SOI Technology for the GHz Era,”
IBM J. Res. & Dev
.
46
, No. 2/3, 121 (2002).
M. Ieong, J. Kedzierski, Z. Ren, B. Doris, T. Kanarsky, and H.-S. P. Wong, “Ultra-Thin Silicon Channel Single- and Double-Gate MOSFETs,”
Extended Abstracts of the Conference on Solid State Devices and Materials
, 2002, p. 136.
M. Ieong, J. Kedzierski, Z. Ren, B. Doris, and E. Nowak, “Opportunities of Ultrathin Channel Single- and Multiple-Gate MOSFETs,”
Proceedings of the Conference on Ultimate Integration in Silicon (ULIS)
, 2003, p. 69.
J. Chu, H. Chen, K. A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and H.-S. P. Wong, “Characteristics and Device Design of Sub-100 nm Strained Si n- and pMOSFETs,”
Symp. VLSI Technol
., p. 8-99 (2002).
K. W. Guarini, P. M. Solomon, Y. Zhang, K. K. Chan, E. C. Jones, G. M. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, J. J. Bucchignano, C. Cabral, Jr., C. Lavoie, V. Ku, D. C. Boyd, K. S. Petrarca, I. V. Babich, J. Treichler, P. M. Kozlowski, J. S. Newbury, C. P. D'Emic, R. Sicina, and H.-S. P. Wong, “Triple-Self-Aligned, Planar Double-Gate MOSFETs: Devices and Circuits,”
IEDM Tech. Digest
, p. 425 (2001).
X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub 50-nm FinFET: PMOS,”
IEDM Tech. Digest
, p. 67 (1999).
K. Guarini and H.-S. P. Wong, “Wafer Bonding for High Performance Logic Applications,”
Wafer Bonding: Applications and Technology
, M. Alexe and U. Goesele, Eds., Springer-Verlag, Berlin, 2004, p. 157.
J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl, “Interconnect Limits on Gigascale Integration (GSI) in the 21st Century,”
Proc. IEEE
89
, 305 (2001).
R. Ho, K. W. Mai, and M. A. Horowitz, “Future of Wires,”
Proc. IEEE
89
, 490 (2001).
Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2004; see
http://public.itrs.net/
.
S. Oktyabrsky, J. Castracane, and A. E. Kaloyeros, “Materials, Components and Integration Technologies for Optical Interconnects,”
Proc. SPIE
4652
, 213 (2002).
K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and System-on-Chip Integration,”
Proc. IEEE
89
, No. 5, 602 (2001).
K. W. Guarini, A. T. Topol, M. Ieong, R. Yu, L. Shi, M. R. Newport, D. J. Frank, D. V. Singh, G. M. Cohen, S. V. Nitta, D. C. Boyd, P. A. O'Neil, S. L. Tempest, H. B. Pogge, S. Purushothaman, and W. E. Haensch, “Electrical Integrity of State-of-the-Art 0.13
μ
m SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,”
IEDM Tech. Digest
, p. 943 (2002).
S. F. Al-sarawi, D. Abbott, and P. D. Franzon, “A Review of 3-D Packaging Technology,”
IEEE Trans. Components, Pkg. & Manuf. Technol. B
21
, 1 (1998).
M. Ieong, K. W. Guarini, V. Chan, K. Bernstein, R. Joshi, J. Kedzierski, and W. Haensch, “Three Dimensional CMOS Devices and Integrated Circuits,”
Proceedings of the IEEE Custom Integrated Circuits Conference
, 2003, pp. 207–213.
Y. Uemoto, E. Fujii, A. Nakamura, and K. Senda, “A High Performance Stacked CMOS SRAM Cell by Solid Phase Growth Technique,”
Symp. VLSI Technol
., p. 21 (1990).
T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, “Three-Dimensional IC's Having Four Stacked Active Device Layers,”
IEDM Tech. Digest
, p. 837 (1989).
D. J. Frank, “Power Constrained Device and Technology Design for the End of Scaling,”
IEDM Tech. Digest
, p. 643 (2002).
S. Matsuo, T. Nakahara, K. Tateno, H. Tsuda, and T. Kurokawa, “Hybrid Integration of Smart Pixel with Vertical-Cavity Surface-Emitting Laser Using Polyimide Bonding,”
Proceedings of the Topical Meeting on Spatial Light Modulators
, 1997, p. 39.
J. Forthun and C. Belady, “3-D Memory for Improved System Performance,”
Proceedings of the International Electron Packaging Conference
, 1992, p. 667.
R. E. Terrill, “Aladdin: Packaging Lessons Learned,”
Proceedings of the International Conference on Multichip Modules
, 1995, p. 7.
S. Jagar, M. Chan, M. C. Poon, H. Wang, M. Qin, P. K. Ko, and Y. Wang, “Single Grain Thin-Film-Transistor (TFT) with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization,”
IEDM Tech. Digest
, p. 293 (1999).
S. Pae, T. Su, J. P. Denton, and G. W. Neudeck, “Multiple Layers of Silicon-on-Insulator Islands Fabrication by Selective Epitaxial Growth,”
IEEE Electron Device Lett.
20
, 194 (1999).
L. Xue, C. C. Liu, and S. Tiwari, “Multi-Layers with Buried Structures (MLBS): An Approach to Three Dimensional Integration,”
Proceedings of the IEEE International SOI Conference
, 2001, p. 117.
V. W. C. Chan, P. C. H. Chan, and M. Chan, “Three-Dimensional CMOS SOI Integrated Circuit Using High Temperature Metal-Induced Lateral Crystallization,”
IEEE Trans. Electron Devices
48
, 1394 (2001).
A. W. Topol, B. K. Furman, K. W. Guarini, L. Shi, G. M. Cohen, and G. F. Walker, “Enabling Technologies for Wafer-Level Bonding of 3D MEMS and Integrated Circuit Structures,”
Proceedings of the 54th Electronic Components and Technology Conference (ECTC)
, 2004, p. 931.
P. Morrow, M. J. Kobrinsky, S. Ramanathan, C.-M. Partk, M. Harmes, V. Ramachandrarao, H.-M. Park, G. Kloster, S. List, and S. Kim, “Wafer-Level 3D Interconnects Via Cu Bonding,”
Proceedings of the UC Berkeley Extension Advanced Metallization Conference (AMC)
, 2004;
Mater. Res. Soc. Symp. Proc
,
20
, 125–130 (2005).
K. W. Lee, T. Nakamure, T. Ono, T. Yamada, T. Mizukusa, T. Hashimoto, H. Park, K. T. Kurino, and M. Koyanagi, “Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology,”
IEDM Tech. Digest
, p. 165 (2000).
A. W. Topol, D. C. La Tulipe, L. Shi, S. M. Alam, D. J. Frank, S. E. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. DiMilia, M. T. Robson, E. Duch, M. Farinelli, C. Wang, R. A. Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T. Kwietniak, C. D'Emic, J. Ott, A. M. Young, K. W. Guarini, and M. Ieong, “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),”
IEDM Tech. Digest
, p. 363 (2005).
D. La Tulipe, L. Shi, A. Topol, S. Steen, D. Pfeiffer, D. Posillico, D. Neumayer, S. Goma, J. Vichiconti, J. Rubino, A. Young, and M. Ieong, “Critical Aspects of Layer Transfer and Alignment Tolerances for 3D Integration Processes,”
Proceedings of the International Conference and Exhibition on Device Packaging (IMAPS)
, 2006; to be published in
J. Microelectron. & Electron. Pkg
. (2006).
K. W. Guarini, A. T. Topol, D. V. Singh, D. C. La Tulipe, L. Shi, A. M. Young, A. Alam, D. J. Frank, D. A. Neumayer, J. Vichiconti, R. M. Sicina, R. A. Conti, C. Wang, D. M. Canaperi, L. Deligianni, K. T. Kwietniak, S. E. Steen, M. Robson, G. W. Gibson, D. Posillico, and M. Ieong, “Process Technologies for Three Dimensional Integration,”
Proceedings of the 6th Annual International Conference on Microelectronics and Interfaces
, American Vacuum Society, 2005, p. 212.
K. A. Jenkins and R. L. Franch, “Impact of Self-Heating on Digital SOI and Strained-Silicon CMOS Circuits,”
Proceedings of the IEEE International SOI Conference
, 2003, p. 161.
K. A. Jenkins and K. Rim, “Measurement of the Effect of Self-Heating in Strained-Silicon MOSFETs,”
IEEE Electron Device Lett.
23
, 360 (2002).
L. Su, J. E. Chung, D. A. Antoniadis, K. E. Goodson, and M. I. Flik, “Measurement and Modeling of Self-Heating in SOI NMOSFETS,”
IEEE Trans. Electron Devices
41
, 69 (1994).
A. Rahman and R. Reif, “Thermal Analysis of Three-Dimensional (3-D) Integrated Circuits (ICs),”
Proceedings of the IEEE International Interconnect Conference
, 2001, p. 157.
A. W. Topol, D. C. La Tulipe, L. Shi, S. M. Alam, A. M. Young, D. J. Frank, S. E. Steen, J. Vichiconti, D. Posillico, D. M. Canaperi, S. Medd, R. A. Conti, S. Goma, D. Dimilia, C. Wang, L. Deligianni, M. A. Cobb, K. Jenkins, A. Kumar, K. T. Kwietniak, M. Robson, G. W. Gibson, C. D'Emic, E. Nowak, R. Joshi, K. W. Guarini, and M. Ieong, “Assembly Technology for Three Dimensional Integrated Circuits,”
Proceedings of the VLSI/ULSI Multilevel Interconnection Conference
, 2005, p. III-D.
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