Anna W. Topol IBM Systems and Technology Group, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (atopolus.ibm.com). Dr. Topol joined IBM in 2001 after receiving her doctoral degree in physics from the State University of New York at Albany and a brief period at Suny–Albany as a postdoctoral research associate in the field of thin-film electroluminescent display applications. She first joined the Advanced Interconnect Technology group as a Research Staff Member and worked in the area of layer transfer of back-end-of-line (BEOL) structures, a novel enabling technology for future low-k and/or air-gap-containing interconnect levels. Dr. Topol later joined the Advanced Device group, where she participated in and led a number of semiconductor fabrication technology programs. She was a project leader for a $4.3M government-funded contract on three-dimensional integrated circuits and a technical leader for R&D efforts related to the fabrication of middle-of-the-line (MOL) integrated circuits. Her work focused on developing new materials and processes for MOL circuits and their integration in emerging microelectronic device manufacturing, for which she received an IBM Research Outstanding Technical Contribution Achievement Award in 2004. In February 2002 Dr. Topol joined the IBM STG Alliance strategy group as a Technical Assistant to Dr. Bernard Meyerson (VP, Strategic Alliances and Chief Technologist, STG). Dr. Topol participated in the 2002 Corporate Technology Communication Advisory Council and in 2005 became a member of the Material Research Community Council.

Douglas C. La Tulipe, Jr. IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (dlipus.ibm.com). Mr. La Tulipe is an Advisory Engineer. Since joining IBM in 1984, he has worked on various projects including exploratory III–V device fabrication, advanced lithographic thin-film imaging, and BEOL low-k reactive ion etch processing. Mr. La Tulipe joined the Silicon Technology group in 2004 and began work on 3D integration technology. He is the author of several patents and technical papers.

Leathen Shi IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (leashius.ibm.com). Dr. Shi received his M.S. degree in aeronautics and astronautics and his Sc.D. degree in the field of material engineering from the Massachusetts Institute of Technology in 1978 and 1981, respectively. Since joining the IBM Thomas J. Watson Research Center in 1985, he has worked in a variety of technical areas, including electronic packaging, interconnects, LCD projection monitors, BEOL, CMOS device fabrication and integration, and wafer bonding. Currently, Dr. Shi's major interests are wafer-level 3D device integration and wafer (or substrate) engineering for high-performance electronic devices. He is a member of the IEEE.

David J. Frank IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (djfus.ibm.com). Dr. Frank received a B.S. degree from the California Institute of Technology in 1977 and a Ph.D. degree in physics from Harvard University in 1983. Since graduation, he has worked at the IBM Thomas J. Watson Research Center, where he is a Research Staff Member. His studies have included non-equilibrium superconductivity, III–V devices, and exploring the limits of scaling of silicon technology. His recent work includes the modeling of innovative Si devices, analysis of CMOS scaling issues such as power consumption, discrete dopant effects and short-channel effects associated with high-k gate insulators, exploring various nanotechnologies, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and low-power circuit design. Dr. Frank is an IEEE Fellow; he has served as chairman of the Si Nanoelectronics Workshop and is an associate editor of IEEE Transactions on Nanotechnology. He has authored or co-authored more than 90 technical publications and holds nine U.S. patents.

Kerry Bernstein IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (kbernsteus.ibm.com). Mr. Bernstein is a Senior Technical Staff Member at the IBM Thomas J. Watson Research Center. He is currently responsible for future product technology definition, performance, and application. He received his B.S. degree in electrical engineering from Washington University in St. Louis, joining IBM in 1978. He holds 50 U.S. patents and is a coauthor of three college textbooks and multiple papers on high-speed and low-power CMOS. Mr. Bernstein is currently interested in the area of high-performance, low-power advanced circuit technologies. He is a Senior Member of the IEEE, and is a staff instructor at RUNN/Marine Biological Laboratories, Woods Hole, Massachusetts.

Steven E. Steen IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (ssteenus.ibm.com). Mr. Steen is the team leader for optical patterning and line integrators in the microelectronics research line at the Thomas J. Watson Research Center. He joined IBM in 1997 to help develop Picosecond Imaging Circuit Analysis (PICA) for VLSI characterization and design debug. After the successful commercialization of PICA, he moved on to the challenges of lithography in 2001 and has been leading the imaging efforts in the microelectronics research line. His focus is on developing special lithographic applications to further research into novel devices and structures. Mr. Steen is the author of more than two dozen technical papers; he has several patents pending.

Arvind Kumar IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (arvkumarus.ibm.com). Dr. Kumar received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology. After graduation, he pursued postdoctoral studies in mesoscopic shot noise at CEA Saclay, France. In 1996, he joined the IBM Thomas J. Watson Research Center, where his primary interests have been in semiconductor device physics, modeling, and design.

Gilbert U. Singco IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (gilbtus.ibm.com). Mr. Singco is a development engineer at the IBM Thomas J. Watson Research Center. He worked for several years in nuclear core design and safety analysis before coming to IBM in 1985. Mr. Singco received M.S. degrees in physics and nuclear engineering from the University of Illinois, and an M.S. degree in electrical engineering from the Rensselaer Polytechnic Institute. He writes programming tools and utilities for data analysis of semiconductor measurements.

Albert M. Young IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (yalbertus.ibm.com). Dr. Young received his Ph.D. degree in electrical engineering and computer science in 1994 from the Massachusetts Institute of Technology. He is Program Manager for 3D integration at IBM and is involved in fabrication and infrastructure development activities related to the vertical stacking of silicon integrated circuits. His prior work experience includes 45-nm front-end process integration for the Silicon Technology Department at the Thomas J. Watson Research Center and program management in Emerging Products at the IBM Semiconductor Research and Development Center. He previously worked for several years in the Solid State Division at MIT Lincoln Laboratory.

Kathryn W. Guarini IBM Corporate Division, 294 Route 100, Somers, New York 10598 (kwgus.ibm.com). Dr. Guarini is currently on assignment in IBM Corporate Technology, working on technical assessments for the IBM Technology Team. Before that, she was a Research Staff Member and Manager of the 45-nm Front End Integration group in the Silicon Technology Department at the IBM Thomas J. Watson Research Center. Her research included CMOS device fabrication, three-dimensional integrated circuits, and novel nanofabrication techniques and applications. Dr. Guarini joined the IBM Research Division in 1999 after completing her Ph.D. degree in applied physics at Stanford University.

Meikei Ieong IBM Research Division, 2070 Route 52, Hopewell Junction, New York 12533 (mkieongus.ibm.com). Dr. Ieong received the B.S. degree in electrical engineering from the National Taiwan University, Taiwan, R.O.C., and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Massachusetts, Amherst, in 1993 and 1996, respectively. Since joining IBM in 1995, he has held numerous management and engineering positions in both the research and development organizations. He is currently Senior Manager of the FEOL integration group at the IBM Thomas J. Watson Research Center, Yorktown Heights, New York. His departments are responsible for the 32-nm FEOL integration and metal-gate high-k projects. He is also project leader for the AMD/IBM Research Alliance and the Sony/Toshiba/IBM Research Alliance. Dr. Ieong has published more than one hundred papers in journals and conference proceedings. He has more than fifty patents related to semiconductor technology issued or pending. He was elected a Master Inventor in the IBM Research Division in 2006. In 2001, Dr. Ieong held the position of Adjunct Associate Professor in the Department of Electrical Engineering at Columbia University. He is a committee member of the VLSI Technology Symposium and is also on the executive committee of the IEDM. Dr. Ieong has received an IBM Outstanding Technical Achievement Award, a Research Division Award, a Corporate Award, and two Supplemental Patent Awards.