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IBM Journal of Research and Development
Advanced Silicon Technology   Volume 50, Number 4/5, 2006
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Emerging nanoscale silicon devices taking advantage of nanostructure physics - References

 by T. Hiramoto,
M. Saitoh,
and G. Tsutsui
References

  1. International Technology Roadmap for Semiconductors (ITRS); see http://public.itrs.net/.
  2. M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, “Sub-50 nm Gate Length n-MOSFETs with 10 nm Phosphorus Source and Drain Junctions,” IEDM Tech. Digest, pp. 119–122 (1993).
  3. R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, “30 nm Physical Gate Length CMOS Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays,” IEDM Tech. Digest, pp. 45–48 (2000).
  4. R. Chau, “30nm and 20nm Physical Gate Length CMOS Transistors,” Proceedings of the Silicon Nanoelectronics Workshop, 2001, pp. 2–3.
  5. B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin, “15nm Gate Length Planar CMOS Transistor,” IEDM Tech. Digest, pp. 937–939 (2001).
  6. B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, F.-F. Jamin, L. Shi, W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller, H.-S. P. Wong, and W. Haensch, “Extreme Scaling with Ultra-Thin Si Channel MOSFETs,” IEDM Tech. Digest, pp. 267–270 (2002).
  7. H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M. Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, “Sub-10-nm Planar-Bulk-CMOS Devices Using Lateral Junction Control,” IEDM Tech. Digest, pp. 989–991 (2003).
  8. H. Majima, H. Ishikuro, and T. Hiramoto, “Experimental Evidence for Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs,” IEEE Electron Device Lett. 21, No. 8, 396–398 (2000).
  9. H. Majima, Y. Saito, and T. Hiramoto, “Impact of Quantum Mechanical Effects on Design of Nano-Scale Narrow Channel n- and p-Type MOSFETs,” IEDM Tech. Digest, pp. 733–736 (2001).
  10. G. Tsutsui, M. Saitoh, and T. Hiramoto, “Superior Mobility Characteristics in (110)-Oriented Ultra Thin Body pMOSFETs with SOI Thickness Less Than 6 nm,” Symp. VLSI Technol., pp. 76–77 (2005).
  11. G. Tsutsui, M. Saitoh, and T. Hiramoto, “Experimental Study on Superior Mobility in (110)-Oriented UTB SOI pMOSFETs,” IEEE Electron Device Lett. 26, No. 11, 836–838 (2005).
  12. A. Gold, “Electronics Transport Properties of a Two-Dimensional Electron Gas in a Silicon Quantum-Well Structure at Low Temperature,” Phys. Rev. B 35, No. 2, 723–733 (1987).
  13. H. Sakaki, T. Noda, K. Hirakawa, M. Tanaka, and T. Matsusue, “Interface Roughness Scattering in GaAs/AlAs Quantum Wells,” Appl. Phys. Lett. 51, No. 23, 1934–1936 (1987).
  14. H. Irie, K. Kita, K. Kyuno, and A. Toriumi, “In-Plane Mobility Anisotropy and Universality Under Uni-Axial Strains in n- and p-MOS Inversion Layers on (100), (110), and (111) Si,” IEDM Tech. Digest, pp. 225–228 (2004).
  15. K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, “Experimental Study on Carrier Transport Mechanism in Ultrathin-Body SOI n- and p-MOSFETs with SOI Thickness Less Than 5 nm,” IEDM Tech. Digest, pp. 47–50 (2002).
  16. T. Tezuka, S. Nakaharai, Y. Moriyama, N. Sugiyama, and S. Takagi, “Selectively-Formed High Mobility SiGe-on-Insulator pMOSFETs with Ge-Rich Strained Surface Channels Using Local Condensation Technique,” Symp. VLSI Technol., pp. 198–199 (2004).
  17. I. Åberg, C. Ní Chléirigh, O. O. Olubuyide, X. Duan, and J. L. Hoyt, “High Electron and Hole Mobility Enhancements in Thin-Body Strained Si/Strained SiGe/Strained Si Heterostructures on Insulator,” IEDM Tech. Digest, pp. 173–176 (2004).
  18. M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim, “Six-Band k · p Calculation of the Hole Mobility in Silicon Inversion Layers: Dependence on Surface Orientation, Strain, and Silicon Thickness,” J. Appl. Phys. 94, No. 12, 1079–1095 (2003).
  19. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbé, and K. Chan, “A Silicon Nanocrystals Based Memory,” Appl. Phys. Lett. 68, 1377–1379 (1996).
  20. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, “Effects of Traps on Charge Storage Characteristics in Metal-Oxide-Semiconductor Memory Structures Based on Silicon Nanocrystals,” J. Appl. Phys. 84, 2358–2360 (1998).
  21. I. Kim, K. Yanagidaira, and T. Hiramoto, “Scaling of Nano-Crystal Memory Cell by Direct Tungsten Bitline on Self-Aligned Landing Plug Polysilicon Contact,” IEEE Electron Device Lett. 25, No. 5, 265–267 (2004).
  22. Y. Takahashi, M. Nagase, H. Namatsu, K. Kurihara, K. Iwadate, Y. Nakajima, S. Horiguchi, K. Murase, and M. Tabe, “Fabrication Technique for Si Single-Electron Transistor Operating at Room-Temperature,” Electron. Lett. 31, No. 2, 136–137 (1995).
  23. H. Ishikuro and T. Hiramoto, “Quantum Mechanical Effects in the Silicon Quantum Dot in a Single-Electron Transistor,” Appl. Phys. Lett. 71, No. 25, 3691–3693 (1997).
  24. M. Saitoh, T. Saito, T. Inukai, and T. Hiramoto, “Transport Spectroscopy of the Ultrasmall Silicon Quantum Dot in a Single-Electron Transistor,” Appl. Phys. Lett. 79, No. 13, 2025–2027 (2001).
  25. K. Miyaji, M. Saitoh, and T. Hiramoto, “Very Sharp Room-Temperature Negative Differential Conductance in Silicon Single-Hole Transistor with High Voltage Gain,” Appl. Phys. Lett. 88, No. 14, 143505 (2006).
  26. M. Saitoh and T. Hiramoto, “Extension of Coulomb Blockade Region by Quantum Confinement in the Ultrasmall Silicon Dot in a Single-Hole Transistor at Room Temperature,” Appl. Phys. Lett. 84, No. 16, 3172–3174 (2004).
  27. M. Saitoh, H. Harata, and T. Hiramoto, “Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors,” Jpn. J. Appl. Phys. 44, No. 11, L338–L341 (2005).
  28. M. Saitoh, H. Harata, and T. Hiramoto, “Room Temperature Demonstration of Integrated Silicon Single-Electron Transistor Circuits for Current Switching and Analog Pattern Matching,” IEDM Tech. Digest, pp. 187–190 (2004).
  29. M. Saitoh and T. Hiramoto, “Room-Temperature Demonstration of Highly-Functional Single-Hole Transistor Logic Based on Quantum Mechanical Effect,” IEE Electron. Lett. 40, No. 13, 837–838 (2004).
  30. T. Yamasaki and T. Shibata, “Analog Soft-Pattern-Matching Classifier Using Floating-Gate MOS Technology,” IEEE Trans. Neural Networks 14, No. 5, 1257–1265 (2003).


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