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IBM Research: Computer Architecture
Exploratory Systems Research
Volume 50, Number 2/3, 2006
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High-quality ISA synthesis for low-power cache designs in embedded microprocessors - References
by A. C.
Cheng
and G. S.
Tyson
References
T. Mudge, “Power: A First-Class Architectural Design Constraint,”
IEEE Computer
34
, No. 4, 52–58 (2001).
J. Montanaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue, J. Eno, W. Hoeppner, D. Kruckemyer, T. H. Lee, P. C. M. Lin, L. Madden, D. Murray, M. H. Pearce, S. Santhanam, K. J. Snyder, R. Stephany, and S. C. Thierauf, “A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor,”
IEEE J. Solid-State Circuits
31
, No. 11, 1703–1714 (1996).
L. Wu, C. Weaver, and T. Austin, “CryptoManiac: A Fast Flexible Architecture for Secure Communication,”
Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA)
, 2001, pp. 110–119.
N. Clark, H. Zhong, and S. Mahlke, “Processor Acceleration Through Automated Instruction Set Customization,”
Proceedings of the 36th International Symposium on Microarchitecture (MICRO)
, 2003, pp. 129–140.
N. Kadri, S. Niar, and A. R. Baba-Ali, “Impact of Code Compression on the Power Consumption in Embedded Systems,”
Proceedings of the International Conference on Embedded Systems and Applications (ESA)
, 2003, pp. 197–203.
A. Orpaz and S. Weiss, “A Study of CodePack: Optimizing Embedded Code Space,”
Proceedings of the International Symposium on Hardware/Software Codesign (CODES)
, 2002, pp. 103–108.
IBM Corporation, PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors, Software Reference Manual, Publication No. G522-0290–01, 2000.
Y. Xie, W. Wolf, and H. Lekatsas, “A Code Decompression Architecture for VLIW Processors,”
Proceedings of the 34th International Symposium on Microarchitecture (MICRO)
, 2001, pp. 66–75.
L. Benini, A. Macii, E. Macii, and M. Poncino, “Selective Instruction Compression for Memory Energy Reduction in Embedded Systems,”
Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED)
, 1999, pp. 206–211.
H. Lekatsas, J. Henkel, and W. Wolf, “Code Compression for Low Power Embedded System Design,”
Proceedings of the 37th Design Automation Conference (DAC)
, 2000, pp. 294–299.
S. K. Debray, W. Evans, R. Muth, and B. D. Sutter, “Compiler Techniques for Code Compaction,”
ACM Trans. Program. Lang. & Syst.
22
, No. 2, 378–415 (2000).
J. Lau, S. Schoenmackers, T. Sherwood, and B. Calder, “Reducing Code Size with Echo Instructions,”
Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES)
, 2003, pp. 84–94.
R. E. Gonzalez, “Xtensa: A Configurable and Extensible Processor,”
IEEE Micro
20
, No. 2, 60–70 (2000).
P. Faraboschi, G. Brown, J. A. Fisher, G. Desoli, and F. Homewood, “Lx: A Technology Platform for Customizable VLIW Embedded Processing,”
Proceedings of the International Symposium on Computer Architecture (ISCA)
, 2000, pp. 203–213.
ARM Limited, ARM7TDMI (Rev. 4) Technical Reference Manual, 2001; see
http://www.arm.com/pdfs/DDI0210B_7TDMI_R4.pdf
.
ARM Limited, Improving ARM Code Density and Performance, 2003; see
http://www.arm.com/pdfs/Thumb-2.pdf
.
MIPS Technologies, MIPS32 Architecture for Programmers, Vol. IV-a: The MIPS16 Application Specific Extension to the MIPS32 Architecture, 2001; see
http://www.mips.com/content/Documentation/MIPSDocumentation/
ProcessorArchitecture/doclibrary
.
STMicroelectronics, ST100 Technical Manual, 2003; see
http://www.st.com/stonline/books/pdf/docs/10071.pdf
.
S. Zammattio, “How to Reduce Time-to-Market for System-on-Chip Design,” ARC International, 2002; see
http://www.arc.com/documentation/whitepapers/
.
A. Krishnaswamy and R. Gupta, “Dynamic Coalescing for 16-Bit Instructions,”
ACM Trans. Embedded Computing Syst.
4
, No. 1, 3–37 (2005).
S. Hines, J. Green, G. Tyson, and D. Whalley, “Improving Program Efficiency by Packing Instructions into Registers,”
Proceedings of the IEEE/ACM International Symposium on Computer Architecture (ISCA)
, 2005, pp. 260–271.
R. Joseph, D. Brooks, and M. Martonosi, “Control Techniques to Eliminate Voltage Emergencies in High Performance Processors,”
Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA)
, 2003, pp. 79–90.
A. Church, “An Unsolvable Problem of Elementary Number Theory,”
Amer. J. Math.
58
, No. 2, 345–363 (1936).
A. Turing, “On Computable Numbers, with an Application to the Entscheidungs Problem,”
Proc. Lond. Math. Soc. Ser. 2
42
, 230–265 (1936).
C. Lefurgy, E. Piccininni, and T. Mudge, “Reducing Code Size with Run-Time Decompression,”
Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA)
, 2000, pp. 218–227.
M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown, “MiBench: A Free, Commercially Representative Embedded Benchmark Suite,”
Proceedings of the 4th International Workshop on Workload Characterization
, 2001, pp. 3–14.
The SimpleScalar-Arm Power Modeling Project, 2004; see
http://www.eecs.umich.edu/~panalyzer
.
Intel Corporation, SA-110 Microprocessor Technical Reference Manual, 2000; see
http://www.acm.uiuc.edu/sigarch/resources/docs/sa110_27805802.pdf
.
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