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IBM Journal of Research and Development
Exploratory Systems Research   Volume 50, Number 2/3, 2006
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Modeling wire delay, area, power, and performance in a simulation infrastructure - References

 by N. P. Carter
and A. Hussain
References

  1. V. Agarwal, M. S. Hrishikesh, S. W. Keckler, and D. Burger, “Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures,” Proceedings of the 27th Annual International Symposium on Computer Architecture, 2000, pp. 248–259.
  2. R. Ho, K. W. Mai, and M. A. Horowitz, “The Future of Wires,” Proc. IEEE 89, No. 4, 490–504 (April 2001).
  3. M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August, “Microarchitectural Exploration with Liberty,” Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002, pp. 271–282.
  4. D. I. August, M. Vachharajani, J. A. Blome, N. Vachharajani, D. A. Penry, and R. Rangan, “Architectural Exploration with Liberty,” Tutorial presentation at the 36th Annual International Symposium on Microarchitecture, 2001; see http://liberty.princeton.edu/News/Tutorials/Micro36/.
  5. The Liberty Research Group; see http://liberty.cs.princeton.edu/.
  6. D. Burger and T. M. Austin, “The SimpleScalar Tool Set, Version 2.0,” Technical Report 1342, Computer Science Department, University of Wisconsin, Madison, WI 53706, 1997.
  7. A. Dhodapkar, C. H. Lim, G. Cai, and W. R. Daasch, “TEM2P2EST: A Thermal Enabled Multi-Model Power/Performance ESTimator,” Proceedings of the International Workshop on Power-Aware Computer Systems, 2000, pp. 112–125.
  8. T. M. Conte, S. Banerjia, S. Y. Larin, K. N. Menezes, and S. W. Sathaye, “Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings,” Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture, 1996, pp. 201–211.
  9. C. Lee, M. Potkonjak, and W. H. Mangione-Smith, “MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems,” Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture, 1997, pp. 330–335.
  10. W. W. Hwu, R. E. Hank, D. M. Gallagher, S. A. Mahlke, D. M. Lavery, G. E. Haab, J. C. Gyllenhaal, and D. I. August, “Compiler Technology for Future Microprocessors,” Proc. IEEE 83, No. 12, 1625–1640 (December 1995).
  11. W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool,” Proceedings of the Asia and South Pacific Design and Automation Conference, 2000, pp. 340–345.
  12. D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” Proceedings of the 27th Annual International Symposium on Computer Architecture, 2000, pp. 83–94.


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