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IBM Journal of Research and Development  
Volume 46, Number 6, 2002
System-on-a-Chip and Packaging
 Table of contents: arrowHTML arrowPDF   This article: HTML arrowPDF    DOI: 10.1147/rd.466.0811 arrowCopyright info
   

Subject index for papers in Volume 46

Each index entry below is accompanied by an author's name and a page number; the author index contains the title of the paper and the names of coauthors, if any.

 
Aluminum
Interconnect opportunities for gigascale integration 		Meindl 245
 
Arithmetic and logical unit design
POWER4 system microarchitecture 		Tendler 5
 
ASICs
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering 		Barth 675
Issues and strategies for the physical design of system-on-a-chip ASICs Bednar 661
The IBM ASIC/SoC methodology—A recipe for first-time success Doerre 649
 
Autonomic computing
Flexible configuration and concurrent upgrade for the IBM eServer z900 		Probst 551
Hardware configuration framework for the IBM eServer z900 Bieswanger 537
Intelligent Resource Director Rooney 567
RAS design for the IBM eServer z900 Alves 503
System control structure of the IBM eServer z900 Baitinger 523
The alternate support element, a high-availability service console for the IBM eServer z900 Valentine 559
 
Built-in self-test (BIST)
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering 		Barth 675
The circuit and physical design of the POWER4 microprocessor Warnock 27
 
Circuit and device technology
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology 		Curran 631
The circuit and physical design of the POWER4 microprocessor Warnock 27
 
Clocking
The circuit and physical design of the POWER4 microprocessor 		Warnock 27
 
CMOS
Beyond the conventional transistor 		Wong 133
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) Mandelman 187
CMOS design near the limit of scaling Taur 213
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics Wu 287
Effect of increasing chip density on the evolution of computer architectures Nair 223
Maintaining the benefits of CMOS scaling when scaling bogs down Nowak 169
New insights into carrier transport in n-MOSFETs Lochtefeld 347
Power-constrained CMOS scaling limits Frank 235
POWER4 system microarchitecture Tendler 5
Process modeling for future technologies Law 339
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation Agnello 317
Reliability limits for the gate insulator in CMOS technology Stathis 265
SOI technology for the GHz era Shahidi 121
The circuit and physical design of the POWER4 microprocessor Warnock 27
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
Why BiCMOS and SOI BiCMOS? Ning 181
 
Codes and coding
IBM eServer z900 system microcode verification by simulation: The virtual power-on process 		Koerner 587
z/CECSIM: An efficient and comprehensive microcode simulator for the IBM eServer z900 von Buttlar 607
 
Computer architecture
Development and attributes of z/Architecture 		Plambeck 367
Flexible configuration and concurrent upgrade for the IBM eServer z900 Probst 551
Hardware configuration framework for the IBM eServer z900 Bieswanger 537
IBM eServer z900 I/O subsystem Stigliani 421
System control structure of the IBM eServer z900 Baitinger 523
The microarchitecture of the IBM eServer z900 processor Schwarz 381
 
Computer organization and design
A power, packaging, and cooling overview of the IBM eServer z900 		Singh 711
POWER4 system microarchitecture Tendler 5
 
Computer system availability
The alternate support element, a high-availability service console for the IBM eServer z900 		Valentine 559
 
Cooling
An advanced multichip module (MCM) for high-performance UNIX servers 		Knickerbocker 779
Design and analysis of a scheme to mitigate condensation on an assembly used to cool a processor module Ellsworth 753
High-end server low-temperature cooling Schmidt 739
 
Copper
Interconnect opportunities for gigascale integration 		Meindl 245
Reliability limits for the gate insulator in CMOS technology Stathis 265
 
Damascene process
Beyond the conventional transistor 		Wong 133
 
Device design
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology 		Curran 631
 
Dielectrics
Beyond the conventional transistor 		Wong 133
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics Wu 287
Interconnect opportunities for gigascale integration Meindl 245
Maintaining the benefits of CMOS scaling when scaling bogs down Nowak 169
Power-constrained CMOS scaling limits Frank 235
SOI technology for the GHz era Shahidi 121
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
 
ESCON architecture
IBM eServer z900 I/O subsystem 		Stigliani 421
 
Etching
Beyond the conventional transistor 		Wong 133
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) Mandelman 187
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation Agnello 317
 
Fault tolerance
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology 		Bossen 77
 
Films, metal
Beyond the conventional transistor 		Wong 133
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation Agnello 317
 
Films, oxide
Beyond the conventional transistor 		Wong 133
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation Agnello 317
 
Finite element analysis
Design and analysis of a scheme to mitigate condensation on an assembly used to cool a processor module 		Ellsworth 753
 
I/O devices, systems, and technology
Coupling I/O channels for the IBM eServer z900: Reengineering required 		Gregg 461
FCP for the IBM eServer zSeries systems: Access to distributed storage Adlung 487
Hierarchical indexing data structure method for verifying the functionality of the STI-to-PCI bridge chips of the IBM eServer z900 Silverio 617
Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification Kayser 597
IBM eServer z900 I/O subsystem Stigliani 421
Self-timed interface of the input/output subsystem of the IBM eServer z900 Hoke 447
zSeries features for optimized sockets-based messaging: HiperSockets and OSA-Express Baskey 475
 
IBM eServer z900
Coupling I/O channels for the IBM eServer z900: Reengineering required 		Gregg 461
Development and attributes of z/Architecture Plambeck 367
FCP for the IBM eServer zSeries systems: Access to distributed storage Adlung 487
First- and second-level packaging for the IBM eServer z900 Harrer 397
Flexible configuration and concurrent upgrade for the IBM eServer z900 Probst 551
Hardware configuration framework for the IBM eServer z900 Bieswanger 537
Hierarchical indexing data structure method for verifying the functionality of the STI-to-PCI bridge chips of the IBM eServer z900 Silverio 617
Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification Kayser 597
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology Curran 631
IBM eServer z900 I/O subsystem Stigliani 421
IBM eServer z900 system microcode verification by simulation: The virtual power-on process Koerner 587
Intelligent Resource Director Rooney 567
RAS design for the IBM eServer z900 Alves 503
Self-timed interface of the input/output subsystem of the IBM eServer z900 Hoke 447
System control structure of the IBM eServer z900 Baitinger 523
The alternate support element, a high-availability service console for the IBM eServer z900 Valentine 559
The microarchitecture of the IBM eServer z900 processor Schwarz 381
z/CECSIM: An efficient and comprehensive microcode simulator for the IBM eServer z900 von Buttlar 607
zSeries features for optimized sockets-based messaging: HiperSockets and OSA-Express Baskey 475
 
Insulators
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics 		Wu 287
Interconnect opportunities for gigascale integration Meindl 245
Power-constrained CMOS scaling limits Frank 235
Process modeling for future technologies Law 339
Reliability limits for the gate insulator in CMOS technology Stathis 265
 
Integrated circuit design
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) 		Mandelman 187
CMOS design near the limit of scaling Taur 213
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics Wu 287
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology Bossen 77
Infrastructure requirements for a large-scale, multi-site VLSI development project Rodgers 87
Maintaining the benefits of CMOS scaling when scaling bogs down Nowak 169
New insights into carrier transport in n-MOSFETs Lochtefeld 347
Power-constrained CMOS scaling limits Frank 235
POWER4 system microarchitecture Tendler 5
Reliability limits for the gate insulator in CMOS technology Stathis 265
SOI technology for the GHz era Shahidi 121
The circuit and physical design of the POWER4 microprocessor Warnock 27
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
 
Integrated circuits
New insights into carrier transport in n-MOSFETs 		Lochtefeld 347
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
 
Interconnection technology
An advanced multichip module (MCM) for high-performance UNIX servers 		Knickerbocker 779
First- and second-level packaging for the IBM eServer z900 Harrer 397
IBM eServer z900 I/O subsystem Stigliani 421
Interconnect opportunities for gigascale integration Meindl 245
Land grid array sockets for server applications Corbin 763
Reliability limits for the gate insulator in CMOS technology Stathis 265
 
Interfaces
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics 		Wu 287
Process modeling for future technologies Law 339
Reliability limits for the gate insulator in CMOS technology Stathis 265
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
 
Logic
Early analysis tools for system-on-a-chip design 		Darringer 691
 
Logic design and technology
Beyond the conventional transistor 		Wong 133
CMOS design near the limit of scaling Taur 213
Early analysis tools for system-on-a-chip design Darringer 691
Maintaining the benefits of CMOS scaling when scaling bogs down Nowak 169
SOI technology for the GHz era Shahidi 121
 
Management science
Infrastructure requirements for a large-scale, multi-site VLSI development project 		Rodgers 87
 
Materials
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation 		Agnello 317
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
 
Materials technology
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation 		Agnello 317
 
Mathematics
Fast pseudorandom-number generators with modulus 2k or 2k - 1 using fused multiply-add 		Agarwal 97
 
Mathematics (applied)
Fast pseudorandom-number generators with modulus 2k or 2k - 1 using fused multiply-add 		Agarwal 97
 
Mechanical analysis
Interconnect opportunities for gigascale integration 		Meindl 245
 
Mechanical design
A power, packaging, and cooling overview of the IBM eServer z900 		Singh 711
High-end server low-temperature cooling Schmidt 739
Land grid array sockets for server applications Corbin 763
 
Memory (computer) design and technology
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) 		Mandelman 187
Early analysis tools for system-on-a-chip design Darringer 691
POWER4 system microarchitecture Tendler 5
 
Memory, cache
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering 		Barth 675
POWER4 system microarchitecture Tendler 5
 
Memory, random-access
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) 		Mandelman 187
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering Barth 675
SOI technology for the GHz era Shahidi 121
 
Metallurgy
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) 		Mandelman 187
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation Agnello 317
 
Microelectronics
Hierarchical indexing data structure method for verifying the functionality of the STI-to-PCI bridge chips of the IBM eServer z900 		Silverio 617
The microarchitecture of the IBM eServer z900 processor Schwarz 381
 
Microprocessor systems and applications
Effect of increasing chip density on the evolution of computer architectures 		Nair 223
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology Bossen 77
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems Ludden 53
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology Curran 631
POWER4 system microarchitecture Tendler 5
SOI technology for the GHz era Shahidi 121
The circuit and physical design of the POWER4 microprocessor Warnock 27
 
Models and modeling
Hardware configuration framework for the IBM eServer z900 		Bieswanger 537
Process modeling for future technologies Law 339
 
Multichip modules (MCMs)
An advanced multichip module (MCM) for high-performance UNIX servers 		Knickerbocker 779
Design and analysis of a scheme to mitigate condensation on an assembly used to cool a processor module Ellsworth 753
First- and second-level packaging for the IBM eServer z900 Harrer 397
High-end server low-temperature cooling Schmidt 739
 
Multiprocessors
Effect of increasing chip density on the evolution of computer architectures 		Nair 223
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems Ludden 53
POWER4 system microarchitecture Tendler 5
 
Nanoscale structures and devices
Beyond the conventional transistor 		Wong 133
Power-constrained CMOS scaling limits Frank 235
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation Agnello 317
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
 
Noise
A power, packaging, and cooling overview of the IBM eServer z900 		Singh 711
 
Packaging
A power, packaging, and cooling overview of the IBM eServer z900 		Singh 711
An advanced multichip module (MCM) for high-performance UNIX servers Knickerbocker 779
Design and analysis of a scheme to mitigate condensation on an assembly used to cool a processor module Ellsworth 753
First- and second-level packaging for the IBM eServer z900 Harrer 397
High-end server low-temperature cooling Schmidt 739
Land grid array sockets for server applications Corbin 763
POWER4 system microarchitecture Tendler 5
 
Parallel processing
Coupling I/O channels for the IBM eServer z900: Reengineering required 		Gregg 461
Intelligent Resource Director Rooney 567
 
Performance analysis
Early analysis tools for system-on-a-chip design 		Darringer 691
 
Photoresists
Beyond the conventional transistor 		Wong 133
 
Power supplies
A power, packaging, and cooling overview of the IBM eServer z900 		Singh 711
 
Process control and development
Process modeling for future technologies 		Law 339
 
Reduced-instruction-set computers (RISC)
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology 		Bossen 77
POWER4 system microarchitecture Tendler 5
 
Reliability
A power, packaging, and cooling overview of the IBM eServer z900 		Singh 711
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics Wu 287
RAS design for the IBM eServer z900 Alves 503
Reliability limits for the gate insulator in CMOS technology Stathis 265
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
 
Servers
A power, packaging, and cooling overview of the IBM eServer z900 		Singh 711
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology Bossen 77
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems Ludden 53
High-end server low-temperature cooling Schmidt 739
IBM eServer z900 I/O subsystem Stigliani 421
POWER4 system microarchitecture Tendler 5
zSeries features for optimized sockets-based messaging: HiperSockets and OSA-Express Baskey 475
 
Silicides
New insights into carrier transport in n-MOSFETs 		Lochtefeld 347
 
Silicon
Beyond the conventional transistor 		Wong 133
Maintaining the benefits of CMOS scaling when scaling bogs down Nowak 169
New insights into carrier transport in n-MOSFETs Lochtefeld 347
Why BiCMOS and SOI BiCMOS? Ning 181
 
Silicon dioxide
Beyond the conventional transistor 		Wong 133
Maintaining the benefits of CMOS scaling when scaling bogs down Nowak 169
New insights into carrier transport in n-MOSFETs Lochtefeld 347
Process modeling for future technologies Law 339
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation Agnello 317
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
 
Silicon oxidation
New insights into carrier transport in n-MOSFETs 		Lochtefeld 347
 
Simulation
Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification 		Kayser 597
IBM eServer z900 system microcode verification by simulation: The virtual power-on process Koerner 587
z/CECSIM: An efficient and comprehensive microcode simulator for the IBM eServer z900 von Buttlar 607
 
Storage (computer) devices and systems
Effect of increasing chip density on the evolution of computer architectures 		Nair 223
FCP for the IBM eServer zSeries systems: Access to distributed storage Adlung 487
 
System-on-a-chip (SoC)
Early analysis tools for system-on-a-chip design 		Darringer 691
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering Barth 675
Issues and strategies for the physical design of system-on-a-chip ASICs Bednar 661
The IBM ASIC/SoC methodology—A recipe for first-time success Doerre 649
 
Thermal conduction module (TCM)
POWER4 system microarchitecture 		Tendler 5
 
Transistors
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) 		Mandelman 187
CMOS design near the limit of scaling Taur 213
New insights into carrier transport in n-MOSFETs Lochtefeld 347
Power-constrained CMOS scaling limits Frank 235
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? Osburn 299
Why BiCMOS and SOI BiCMOS? Ning 181
 
Transistors, bipolar
Why BiCMOS and SOI BiCMOS? 		Ning 181
 
Tunneling
Power-constrained CMOS scaling limits 		Frank 235
 
VLSI
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) 		Mandelman 187
CMOS design near the limit of scaling Taur 213
Effect of increasing chip density on the evolution of computer architectures Nair 223
Infrastructure requirements for a large-scale, multi-site VLSI development project Rodgers 87
Maintaining the benefits of CMOS scaling when scaling bogs down Nowak 169
SOI technology for the GHz era Shahidi 121
Why BiCMOS and SOI BiCMOS? Ning 181
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