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IBM Journal of Research and Development 
Volume 46, Number 6, 2002
System-on-a-Chip and Packaging
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The IBM ASIC/SoC methodology—A recipe for first-time success - Author Bios

by G. W. Doerre and D. E. Lackey

Biographical sketches of authors

George W. Doerre IBM Microelectronics Division, East Fishkill facility, Hopewell Junction, New York 12533 (doerrg@us.ibm.com). Mr. Doerre manages ASIC and EDA strategy for IBM Microelectronics Product Development. In 1980, he joined IBM in Burlington, Vermont, working on advanced DRAM development. Since then, he has held management positions in VLSI product and process development and ASIC design methodology development and integration. He holds M.S.E.E./C.S. and M.S. physics degrees from MIT.

David E. Lackey IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (delacke@us.ibm.com). Mr. Lackey is a Senior Technical Staff Member in the IBM ASIC Product Development group, responsible for ASIC methodology development. In 1978 he joined IBM in Poughkeepsie, New York, in the Mid-Hudson Valley Development Laboratory. Since 1994, Mr. Lackey has developed leading-edge design methodologies for IBM and external ASIC designs. He received a B.S.E.E. degree from Rensselaer Polytechnic Institute in 1978 and an M.S.C.E. degree from Syracuse University in 1983. He is a member of IEEE and Eta Kappa Nu.