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Volume 46, Number 6, 2002
System-on-a-Chip and Packaging |
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Table of contents:
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This article:
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Early analysis tools for system-on-a-chip design - References
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by
J. A. Darringer, R. A. Bergamaschi, S. Bhattacharya, D. Brand, A. Herkersdorf, J. K. Morrell, I. I. Nair, P. Sagmeister, and Y. Shin
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References
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“CoreWare Design Program and Cores,” LSI Logic Corporation, http://www.lsilogic.com/products/coreware/.
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“Design Reuse Cuts Time to Market,” Royal Philips Electronics, http://www.semiconductors.philips.com/technology/designreuse/index.html.
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IBM Blue Logic Technology, http://www-3.ibm.com/chips/bluelogic/.
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IBM CoreConnect Bus Architecture White Paper, http://www-3.ibm.com/chips/products/coreconnect/index.html.
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F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B. Tabbara, Hardware–Software Co-Design of Embedded Systems: The Polis Approach, Kluwer Academic Publishers, New York, 1997.
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T. B. Ismail, M. Abid, and A. A. Jerraya, “COSMOS: A Codesign Approach for Communication Systems,” Proceedings of the Third International Workshop on Hardware/Software Codesign, Grenoble, 1994, pp. 17–24.
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A. Österling, Th. Benner, R. Ernst, D. Herrmann, Th. Scholz, and W. Ye, “The COSYMA System,” Hardware/Software Co-Design: Principles and Practice, Kluwer Academic Publishers, New York, 1997.
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Jörn W. Janneck and Martin Naedele, “Modeling Hierarchical and Recursive Structures Using Parametric Petri Nets,” Proceedings of the Conference on High Performance Computing (HPC'99), San Diego, 1999, pp. 445–452.
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Edward A. Lee, “Overview of the Ptolemy Project,” Technical Memorandum UCB/ERL M01/11, University of California, Berkeley, March 6, 2001; http://ptolemy.eecs.berkeley.edu/.
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M. C. W. Geilen and J. P. M. Voeten, “Object-Oriented Modelling and Specification using SHE,” Proceedings of the First International Symposium on Visual Formal Methods (VFM'99, satellite to CONCUR'99), D. Bosnacki, S. Mauw, and T. Willemse, Eds., Eindhoven University of Technology, The Netherlands, 1999, pp. 16–24.
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Methodology Backgrounder, Virtual Component Co-Design (VCC), White Paper, Cadence Design Systems, 1999.
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D. Verkest, K. Van Rompaey, I. Bolsens, and H. De Man, “CoWare: A Design Environment for Heterogeneous Hardware/Software Systems,” Design Automation for Embedded Systems 1, No. 4, 357–386 (October 1996).
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Seamless HW/SW Co-Verification, Platform-Based SoC Design & Verification, datasheet, Mentor Graphics; http://www.mentor.com/platform_ex/platform_ex_ds.html.
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G. Logothetis and K. Schneider, “A New Approach to the Specification and Verification of Real-Time Systems,” Proceedings of the Euromicro Conference on Real-Time Systems, IEEE Computer Society, Delft, The Netherlands, June 2001, pp. 171–180.
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SES/Workbench Version 3.3, Introductory Training Course, Scientific and Engineering Software, Inc. (now HyPerformix, Inc.), 2001; http://www.hyperformix.com/.
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The Artifex Language, ARTIS Software Corporation, White Paper, 2001; http://www.artis-software.com/.
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eArchitect Architectural Exploration, product overview; http://www.innoveda.com.
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Virtual Socket Interface Alliance, “VSI Alliance Architecture Document,” Version 1.0, VSI Alliance, 1997; http://www.vsi.com/.
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Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronaldo Wagner, Colleen Fellenz, William R. Lee, Foster White, Michael Muhlada, and Jean-Marc Daveau, “Automating the Design of SOCs Using Cores,” IEEE Design & Test of Computers 18, No. 5, 32–45 (September/October 2001).
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Fibre Channel—Overview of the Technology, Fibre Channel Industry Association; http://www.fibrechannel.com/technology/index.master.html.
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iSCSI for Storage Networking, Storage Networking Industry Association Storage Forum White Paper; http://www.snia.org/.
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Functional specification of SystemC 2.0; http://www.systemc.org/.
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J. Y. Sayah, R. Gupta, D. Sherlekar, P. S. Honsinger, S. W. Bollinger, H.-H. Chen, S. DasGupta, E. P. Hsieh, E. J. Hughes, A. D. Huber, Z. M. Kurzum, V. B. Rao, T. Tabtieng, V. Valijan, D. Y. Yang, and J. Apte, “Design Planning for High-Performance ASICs,” IBM J. Res. & Dev. 40, No. 4, 431–452 (1996).
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F. N. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Trans. VLSI 2, No. 4, 446–455 (1994).
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T. D. Givargis, F. Vahid, and J. Henkel, “A Hybrid Approach for Core-Based System-Level Power Modeling,” Proceedings of the Asia South Pacific Design Automation Conference, January 2000, pp. 141–145.
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