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Volume 46, Number 6, 2002
System-on-a-Chip and Packaging |
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Table of contents:
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This article:
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Issues and strategies for the physical design of system-on-a-chip ASICs - References
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by
T. R. Bednar, P. H. Buffet, R. J. Darden, S. W. Gould, and P. S. Zuchowski
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References
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T. R. Bednar, R. A. Piro, D. W. Stout, L. Wissel, and P. S. Zuchowski, “Technology-Migratable ASIC Library Design,”
IBM J. Res. & Dev. 40, No. 4, 377–386 (1996).
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J. Dreibelbis, J. Barth, Jr., R. Kho, and H. Kalter, “An ASIC Library Granular DRAM Macro with Built-In Self Test,”
IEEE International Solid State Circuits Conference, Digest of Technical Papers,
1998, pp. 74–75.
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J. Dreibelbis, J. Barth, Jr., H. Kalter, and R. Kho, “Processor Based Built In Self Test for Embedded DRAM,” IEEE J. Solid State Circuits 33, No. 11, 1731–1740 (1998).
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J. E. Barth, Jr., J. H. Dreibelbis, E. A. Nelson, D. L. Anand, G. Pomichter, P. Jakobsen, M. R. Nelms, J. Leach, and G. M. Belansek, “Embedded DRAM Design and Architecture for the IBM 0.11-µm ASIC Offering,” IBM J. Res. & Dev. 46, No. 6, 675–689 (2002, this issue).
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M. R. Ouellette, D. L. Anand, and P. Jakobsen, “Shared Fuse Macro for Multiple Embedded Memory Devices with Redundancy,”
Proceedings of the IEEE Custom Integrated Circuits Conference,
2001, pp. 191–194.
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Patrick H. Buffet, Joseph Natonio, Robert A. Proctor, Yu H. Sun, and Gulsun Yasar, “Methodology for I/O Cell Placement and Checking in ASIC Designs Using Area-Array Power Grid,” IBM MicroNews 6, No. 3, 7–9 (2000).
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A. E. Ruehli and A. C. Cangellaris, “Progress in the Methodologies for the Electrical Modeling of Interconnects and Electronic Packages,”
Proc. IEEE 89, No. 5,
740–771 (2001).
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W. D. Becker, J. Eckhardt, R. W. Frech, G. A. Katopis, E. Klink, M. F. McAllister, T. G. McNamara, P. Muench, S. R. Richter, and H. H. Smith, “Modeling, Simulation, and Measurement of Mid-Frequency Simultaneous Switching Noise in Computer Systems,”
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D. J. Herrell and B. Beker, “Modeling of Power Distribution Systems for High-Performance Microprocessors,”
IEEE Trans. Adv. Packaging 22, No. 3, 240–248 (1999).
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Alex Waizman and Chee-Yee Chung, “Resonant Free Power Network Design Using Extended Adaptive Voltage Positioning (EAVP) Methodology,”
IEEE Trans. Adv. Packaging 24, No. 3,
236–244 (2001).
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P. H. Buffet, J. Natonio, R. A. Proctor, Y. H. Sun, and G. Yasar, “Methodology for I/O Cell Placement and Checking in ASIC Designs,”
Proceedings of the IEEE Custom Integrated Circuits Conference, May
2000, pp. 125–128.
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S. R. Nassif and J. Kozhaya, “Multi-Grid Methods for Power Grid Simulation,”
Proceedings of the IEEE International Symposium on Circuits and Systems,
2000, pp. 457–460.
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J. N. Kozhaya, S. R. Nassif, and F. N. Najm, “I/O Buffer Placement Methodology for ASICs,” Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems,
2001, pp. 245–248.
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C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay, and S. S. Sapatnekar, “Steiner Tree Optimization for Buffers. Blockages and Bays,”
Proceedings of the IEEE International Symposium on Circuits and Systems,
2001, pp. 399–402.
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K. M. Carrig, N. T. Gargiulo, R. P. Gregor, D. R. Menard, and H. E. Reindel, “A New Direction in ASIC High-Performance Clock Methodology,”
Proceedings of the IEEE Custom Integrated Circuits Conference,
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593–596.
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D. E. Lackey, “Applying Placement-Based Synthesis for On-Time System-on-a-Chip Design,”
Proceedings of the IEEE Custom Integrated Circuits Conference,
2000, pp. 121–124.
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W. Donath, P. Kudva, L. Stok, P. Villarrubia, L. Reddy, and A. Sullivan, “Transformational Placement and Synthesis,”
Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe,
2000, pp. 194–201.
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