Biographical sketches of authors

Thomas R. Bednar IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (tbednar@us.ibm.com). Mr. Bednar received a B.S. degree in electrical engineering from the University of Notre Dame in 1982 and an M.S. degree in electrical engineering from the University of Vermont in 1988. He joined IBM in Essex Junction in 1982 and has worked on the definition, design, and qualification of several generations of ASIC products and function libraries. Mr. Bednar is currently a Senior Technical Staff Member in ASIC Product Development.

Patrick H. Buffet IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (buffetph@us.ibm.com). Mr. Buffet received a Diplome d'Ingenieur degree from the Institut National Polytechnique de Grenoble, France. He worked with Texas Instruments and Digital Equipment Corporation before joining IBM in 1992. Mr. Buffet has designed integrated circuits and currently performs electrical analysis of die images and packages. He is a member of the IEEE and has served on technical program and standards committees. He has ten filed patent applications and eight others pending.

Randall J. Darden IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (rjdarden@us.ibm.com). Mr. Darden joined IBM in 1983 and has worked in several areas of ASIC design, methodology, and support. He received a B.S. degree in 1982 and an M.S. degree in 1983, both in electrical engineering from Washington State University. He also received the M.S. degree in computer science in 1999 from National Technical University. Mr. Darden is currently a Senior Engineer in the ASIC Layout Services and Software Department; he has interests in ASIC physical design, including hierarchical processing and timing-driven methodologies.

Scott W. Gould IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (swgould@us.ibm.com). Mr. Gould received an M.S. degree in electrical engineering from Syracuse University in 1986, and a B.S. degree in electrical engineering from the University of Maine at Orono in 1983. He is an Advisory Engineer working in the ASIC Physical Design Methodology development group, where he is currently the ASIC physical design methodology team leader, with a focus on technology and core development requirements. He has worked in the areas of ASIC library development, physical design methodology, and FPGA design.

Paul S. Zuchowski IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (paulz@us.ibm.com). Mr. Zuchowski received a B.S. degree in electrical and computer engineering from Clarkson University in 1989. He then joined IBM in Essex Junction. In 1995, he received an M.S. degree in microelectronic manufacturing from Rensselaer Polytechnic Institute. Mr. Zuchowski has worked on full-chip physical verification, physical model generation methodology, physical design methodology, and ASIC product architecture. He is currently a Senior Engineer in ASIC product development.