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Volume 46, Number 6, 2002
System-on-a-Chip and Packaging |
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Table of contents:
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This article:
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Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering - References
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by
J. E. Barth, J. H. Dreibelbis, E. A. Nelson, D. L. Anand, G. Pomichter, P. Jakobsen, M. R. Nelms, J. Leach, and G. M. Belansek
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References
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J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, “Processor Based Built-In Self Test for Embedded DRAM,”
IEEE J. Solid-State Circuits 33, No. 11,
1731–1740 (November
1998).
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T. Yabe, S. Miyano, K. Sato, M. Wada, R. Haga, O. Wada, M. Enkaku, T. Hojyo, K. Mimoto, M. Tazawa, T. Ohkubo, and K. Numata, “A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator,”
IEEE J. Solid-State Circuits 33, No. 11,
1752–1757 (November
1998).
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S. Crowder, R. Hannon, H. Ho, D. Sinitsky, S. Wu, K. Winstel, B. Khan, S. R. Stiffler, and S. S. Iyer, “Integration of Trench DRAM into a High Performance 0.18-µm Logic Technology with Copper BEOL,”
International Electron Devices Meeting, Digest of Technical Papers,
1998, pp.
1017–1020.
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T. Obremski, “Advanced Non-Concurrent BIST Architecture for Deep Sub-Micron Embedded DRAM Macros,” Ph.D. Dissertation, University of Vermont, Burlington, May 2001.
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N. Watanabe, F. Morishita, Y. Taito, A. Yamazaki, T. Tanizaki, K. Dosaka, Y. Morooka, F. Igaue, K. Furue, Y. Nagura, T. Komoike, T. Morihara, A. Hachisuka, K. Arimoto, and H. Ozaki, “An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced on Chip Tester,”
IEEE International Solid-State Circuits Conference, Digest of Technical Papers,
2001, pp.
388–389, 469.
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R. H. Dennard, “Field Effect Transistor Memory,” U.S. Patent 3,387,286, June 4, 1968.
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E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for LSI Testability,”
J. Design Automat. Fault-Tolerant Comput. 2,
165–178 (May
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J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, “Built-In Self Test for Embedded DRAM,”
Proceedings of the IEEE North Atlantic Test Workshop, West Greenwich, RI,
1997, pp.
19–27.
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R. McConnell, U. Moller, and D. Richter, “How We Test Siemens' Embedded DRAM Cores,”
Proceedings of the International Test Conference,
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1120–1125.
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R. Aitken, “On-Chip Versus Off-Chip Test: An Artificial Dichotomy,”
Proceedings of the International Test Conference,
1998, p.
1146.
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J. Dreibelbis, J. Barth Jr., R. Kho, and T. Kalter, “An ASIC Library Granular DRAM Macro with Built-In Self Test,”
IEEE International Solid-State Circuits Conference, Digest of Technical Papers,
1998, pp.
74–75.
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H. A. Bonges III, R. D. Adams, A. J. Allen, R. Flaker, K. S. Gray, E. L. Hedberg, W. T. Holman, G. M. Lattimore, D. A. Lavalette, K. Y. T. Nguyen, and A. L. Roberts, “A 576K 3.5ns Access BiCMOS ECL Static Ram with Array Built-in Self Test,”
IEEE J. Solid-State Circuits 27, No. 4,
649–656 (April 1992).
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P. Jakobsen, J. Dreibelbis, G. Pomichter, D. Anand, J. Barth, M. Nelms, J. Leach, and G. Belansek, “Embedded DRAM Built In Self Test and Methodology for Test Insertion,”
Proceedings of the International Test Conference,
2001, pp. 975–984
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