Biographical sketches of authors

John E. Barth Jr. IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (jbarth@us.ibm.com). Mr. Barth received the B.S.E.E. degree from Northeastern University in 1987, and the M.S.E.E. degree from National Technological University in 1992. During his B.S. degree work he was a co-op student from 1984 to 1985 at the Timeplex Development Laboratory in Rochelle Park, New Jersey, where he wrote data communications and network monitoring software. He was also a co-op student in 1986 at the IBM Development Laboratory in Essex Junction, Vermont, where he was involved in the design and characterization of the 1Mb DRAM product. After receiving his B.S. degree, Mr. Barth joined IBM at the Development Laboratory in Essex Junction, and was involved in the design of a 16Mb DRAM product featuring embedded ECC and SRAM cache. Following this, he worked on array design for the 16/18Mb DRAM product. In 1994 he began work in his current field of wide-I/O, high-performance DRAM macros for embedded applications.

Jeffrey H. Dreibelbis IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (jdreib@us.ibm.com). Mr. Dreibelbis received the B.S. degree in electrical engineering from Lehigh University in 1973. Upon graduation, he joined the U.S. Air Force, where he served as a Communications Electronics Engineer for the USAF Communications Service at Griffiss AFB, Rome, New York, until 1977. In 1977 he joined the semiconductor development laboratory of the IBM Microelectronics Division in Essex Junction, Vermont, where he first worked in n-MOS SRAM and DRAM product design. He later became a key developer in CMOS SRAM projects, CMOS commodity DRAM designs, and embedded SRAM macros. He is currently a Senior Technical Staff Member in the IBM Advanced Memory Design group, working on the development of embedded DRAM macros for IBM ASIC offerings. Mr. Dreibelbis is a member of Tau Beta Pi, Eta Kappa Nu, and the IEEE.

Erik A. Nelson IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (eanelson@us.ibm.com). Mr. Nelson received the B.S.Ch.E. degree from Cornell University. He joined IBM in East Fishkill, New York, in 1982, working on wafer fabrication process development for bipolar transistor products. In addition to process development, he has experience in electrical characterization and wafer manufacturing. Since 1993, Mr. Nelson has worked on DRAM product development in Essex Junction, Vermont. After working with IBM development partners on 64Mb to 256Mb commodity DRAMs, he turned his attention to embedded DRAM, contributing to product development and introduction to manufacturing for SA-27E and CU-11 products.

Darren L. Anand IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (danand@us.ibm.com). Mr. Anand received a B.S.C.E. degree from Clarkson University in 1997. After his junior year at Clarkson, he interned with IBM Microelectronics in Essex Junction, Vermont, in 1996, working in the PowerPC development group. In 1997, he became a full-time employee of IBM Microelectronics in Essex Junction, working on high-performance 16Mb SGRAM design. In 1998, he began work in his current field, high-performance embedded DRAM macro design. In addition to eDRAM data path and array design, Mr. Anand has worked on a 144Mb SRAM replacement based on the eDRAM macro and has done extensive work on eFuse development.

Gerald (Gary) Pomichter IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (garypp@us.ibm.com). Mr. Pomichter received his B.S.C.E. degree from Clarkson University in 1990. He subsequently joined the IBM Workstation Division in Kingston, New York, where he was involved with high-speed 3D workstation graphics controller design. After moving to the IBM Microelectronics Division in Essex Junction, Vermont, in 1994, he helped to design the IBM family of synchronous graphics RAMs. Since 1998, he has been working on the IBM wide-I/O, high-performance DRAM macros for embedded applications.

Peter Jakobsen IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (jakobsp@us.ibm.com). Mr. Jakobsen received the B.S.C.E. degree from Pennsylvania State University in 1997. During his B.S. degree work he was a co-op student with IBM in Essex Junction, Vermont, where he tested 4Mb SGRAM and wrote data extraction software to analyze circuit simulation data. In 1998 he joined the IBM SDRAM development group which later developed RAMBUS. In 2000 he began work in his current field of wide-I/O, high-performance DRAM macros for embedded applications.

Michael R. Nelms IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (mnelms@us.ibm.com). Mr. Nelms received a B.S.E.E. degree from the University of Vermont in 1998. During his B.S. degree work, he was an intern at Game Financial Corporation in Plymouth, Minnesota, writing and maintaining software for a customer call center. He also was a co-op student at IBM in Essex Junction, Vermont, where he modeled 256MB DIMMs and motherboard configurations. After graduation, he joined IBM in Essex Junction, where he now works on developing embedded DRAM macros for the IBM ASICs program.

Jeffrey Leach (current address unavailable). Mr. Leach received a B.S. degree in computer engineering from Clarkson University in 2000. In 1998 he was a co-op student at GE Power Systems as a Y2K database design engineer. In 1999 he was a co-op student with IBM on the ASIC ROM development team writing software to automate schematic verification. At Clarkson he was a software systems architecture teaching assistant. After receiving his bachelor's degree, Mr. Leach joined the IBM Microelectronics embedded DRAM design team in Essex Junction, Vermont, as a circuit design engineer. He left IBM in November 2001.

George M. Belansek IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (georgeb@us.ibm.com). Mr. Belansek received his B.S.E.E. degree from Pennsylvania State University in 1983, and his M.S.E.E. degree from the University of Vermont in 1990. While an undergraduate, he twice interned with IBM in the Essex Junction, Vermont, facility working in final test and DRAM design. Upon graduation he joined the IBM Microelectronics Division in Essex Junction. Mr. Belansek has held various assignments at IBM, including lead characterization engineer for IBM SRAM products, Project Manager for the IBM graphic memory (SGRAM) product line, and, currently, Design Manager of the high-performance embedded DRAM and SRAM development team.