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     IBM eServer zSeries  
IBM Journal of Research and Development  
Volume 46, Numbers 4/5, 2002
IBM eServer z900
 Table of contents: arrowHTML arrowPDF arrowASCII   This article: arrowHTML arrowPDF arrowASCII arrowCopyright info
   

First- and second-level packaging for the IBM eServer z900 - References

by H. Harrer, H. Pross, T.-M. Winkel, W. D. Becker, H. I. Stoller, M. Yamamoto, S. Abe, B. J. Chamberlin, and G. A. Katopis

References

  1. G. A. Katopis, W. D. Becker, T. R. Mazzawey, H. H. Smith, C. K. Vakirtzis, S. A. Kuppinger, B. Singh, P. C. Lin, J. Bartells, Jr., G. V. Kihlmire, P. N. Venkatachalam, H. I. Stoller, and J. L. Frankel, “MCM Technology and Design for the S/390 G5 System,” IBM J. Res. & Dev. 43, No. 5/6, 621–650 (September/November 1999).
  2. G. A. Katopis and W. D. Becker, “S/390 Cost Performance Considerations for MCM Packaging Choices,” IEEE Trans. Components, Packaging, Manuf. Technol., Part B: Adv. Packaging 21, No. 3, 286–297 (August 1998).
  3. A. Charlesworth, “The Sun Fireplane System Interconnect,” presented at the IEEE Supercomputing 2001 Workshop, Denver, November 2001.
  4. E. Cordero, F. Ferriaolo, M. Floyd, K. Grower, and B. McCredie, “A Synchronous Wave-Pipeline Interface for POWER4,” presented at the IEEE Computer Society HOT CHIPS Workshop, Stanford University, August 15–17, 1999.
  5. M. F. McAllister, H. Harrer, and J. Chen, “Measurements of Signal Transmissions Using a Source Synchronous Wave-Pipeline Interface Across Multiple Interface Structures,” presented at the Fourth Workshop on Signal Propagation of Interconnects, Magdeburg, Germany, May 2000.
  6. J. M. Hoke, P. W. Bond, T. Lo, F. S. Pidala, and G. Steinbrueck, “Self-Timed Interface for S/390 I/O Subsystem Interconnection,” IBM J. Res. & Dev. 43, No. 5/6, 829–846 (September/November 1999).
  7. H. Harrer, D. Kaller, T. W. Winkel, and E. Klink, “Performance Comparison and Coupling Impact of Different Thin Film Structures,” VDE/VDI Proceedings of the Mikroelektronik 97, Munich, March 1997, pp. 333–338.
  8. H. Stoller, S. Ray, E. Perfecto, and T. Wassik, “Evolution of Engineering Change (EC) and Repair Technology in High Performance Multichip Modules at IBM,” Proceedings of the 48th IEEE Conference on Electronic Components and Technology, Seattle, May 1998, pp. 916–921.
  9. R. R. Tummala and E. J. Rymaszewski, Eds., Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989.
  10. T. W. Winkel, E. Klink, R. Frech, H. Virag, S. Böhringer, B. Chamberlin, D. Becker, and W. M. Ma, “Method and Structure for Reducing Power Noise,” Patent No. DE8-1999-0040, IBM Boeblingen, March 1999.
  11. B. Garben and M. F. McAllister, “Novel Methodology for Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards and Verification by Measurements,” Proceedings of the 9th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Scottsdale, AZ, 2000, pp. 69–72.
  12. Sigrity, Inc., SPEED 97; available online at http://www.sigrity.com.
  13. H. H. Smith and G. A. Katopis, “Multireflection Algorithm for Timed Statistical Coupled Noise Checking,” IEEE Trans. Components, Packaging & Manuf. Techn. 19, 503–511 (August 1996).