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by G. G. Shahidi |
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References
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J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Dordrecht, Netherlands, 1991.
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G. G. Shahidi, C. A. Anderson, B. A. Chappell, T. I. Chappell, J. H. Comfort, B. Davari, R. H. Dennard, R. L. Franch, P. A. McFarland, J. S. Neely, T. H. Ning, M. R. Polcari, and J. D. Warnock, A Room Temperature 0.1 µm CMOS on SOI, IEEE Trans. Electron Devices 41, 2405 (1994).
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D. J. Schepis, F. Assaderaghi, D. S. Yee, W. Rausch, R. J. Bolam, A. C. Ajmera, E. Leobandung, S. B. Kulkarni, R. Flaker, D. Sadana, H. J. Hovel, T. Kebede, C. Schiller, S. Wu, L. F. Wagner, M. J. Saccamango, S. Ratanaphanyarat, J. B. Kuang, M. C. Hsieh, K. A. Tallman, R. M. Martino, D. Fitzpatrick, D. A. Badami, M. Hakey, S. F. Chu, B. Davari, and G. G. Shahidi, A 0.25 µm CMOS on SOI and Its Application to 4 Mb SRAM, IEDM Tech. Digest, p. 345 (1997).
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A. Ajmera, J. W. Sleight, F. Assaderaghi, R. Bolam, A. Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, W. Rausch, D. Sadana, D. Schepis, L. F. Wagner, K. Wu, B. Davari, and G. Shahidi, A 0.22 µm CMOSSOI Technology with a Cu BEOL, Symposium on VLSI Technology, Digest of Technical Papers, 1999, p. 15.
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E. Leobandung, E. Barth, M. Sherony, S.-H. Lo, R. Schulz, W. Chu, M. Khare, D. Sadana, D. Schepis, R. Bolam, J. Sleight, F. White, F. Assaderaghi, D. Moy, G. Biery, R. Goldblatt, T.-C. Chen, B. Davari, and G. Shahidi, A 0.18 µm CMOS on SOI Technology, IEDM Tech. Digest, p. 445 (1997).
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P. Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, A. Eckert, L. Hadel, M. Hargrove, J. Herman, L. Lin, R. Mann, E. Maciejewski, S. Narasimha, P. O'Neil, S. Rauch, D. Ryan, J. Toomey, L. Tsou, P. Varekamp, R. Wachnik, T. Wagner, S. Wu, C. Yu, P. Agnello, J. Connolly, S. Crowder, C. Davis, R. Ferguson, A. Sekiguchi, L. Su, R. Goldblatt, and T. C. Chen, A High Performance 0.13 µm SOI CMOS Technology with Cu Interconnects and Low-k BEOL Dielectric, Symposium on VLSI Technology, Digest of Technical Papers, 2000, p. 184.
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S. K. H. Fung, M. Khare, D. Schepis, W. H. Lee, S. H. Ku, H. Park, J. Snare, B. Doris, A. Ajmera, K. P. Muller, P. Agnello, P. Gilbert, and J. Welser, Gate Length Scaling Accelerated to 30nm Regime Using Ultra-Thin Film PD-SOI Technology, IEDM Tech. Digest, p. 629 (2001).
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L. T. Su, J. B. Jacobs, J. E. Chung, and D. A. Antoniadis, Deep-Submicrometer Channel Design in Silicon-on-Insulator (SOI) MOSFET's, IEEE Electron Device Lett. 15, 366 (1994).
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F. Assaderaghi, G. G. Shahidi, L. Wagner, M. Hsieh, M. Pelella, S. Chu, R. H. Dennard, and B. Davari, Transient Pass-Transistor Leakage Current in SOI MOSFET's, IEEE Electron Device Lett. 18, 241 (1997).
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F. Assaderaghi, G. G. Shahidi, M. Hargrove, K. Hathorn, H. Hovel, S. Kulkarni, W. Rausch, D. Sadana, D. Schepis, R. Schulz, D. Yee, J. Sun, R. Dennard, and B. Davari, History Dependence of Non-Fully Depleted (NFD) Digital SOI Circuits, Symposium on VLSI Technology, Digest of Technical Papers, 1996, p. 122.
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G. G. Shahidi, A. Ajmera, F. Assaderaghi, R. J. Bolam, E. Leobandung, W. Rausch, D. Sankus, D. Schepis, L. F. Wagner, K. Wu, and B. Davari, Partially Depleted SOI Technology for Digital Logic, ISSCC Tech. Digest, p. 426 (1999).
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S. K. H. Fung, N. Zamdmer, P. J. Oldiges, J. Sleight, A. Mocuta, M. Sherony, S.-H. Lo, R. Joshi, C. T. Chuang, I. Yang, S. Crowder, T. C. Chen, F. Assaderaghi, and G. Shahidi, Controlling Floating-Body Effects for 0.13 µm and 0.10 µm SOI CMOS, IEDM Tech. Digest, p. 231 (2000).
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T. C. Buchholtz, A. G. Aipperspach, D. T. Cox, N. V. Phan, S. N. Storino, J. D. Strom, and R. R. Williams, A 660 MHz 64b SOI Processor with Cu Interconnects, ISSCC Tech. Digest, p. 88 (2000).
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D. H. Allen, A. G. Aipperspach, D. T. Cox, N. V. Phan, and S. N. Storino, A 0.2 µm 1.8 V SOI 550 MHz 64b PowerPC Microprocessor with Copper Interconnects, ISSCC Tech. Digest, p. 438 (1999).
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D. Stasiak, J. Tran, F. Mounes-Toussl, and S. Storino, A 2nd Generation 440 ps SOI 64b Adder, ISSCC Tech. Digest, p. 288 (2000).
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M. Canada, C. Akrout, D. Cawthron, J. Corr, S. Geissler, R. Houle, P. Kartschoke, D. Kramer, P. McCormick, N. Rohrer, and L. Warriner, A 580 MHz 32 bit PowerPC Microprocessor in 0.12 micron Leff CMOS SOI with Cu Interconnects, ISSCC Tech. Digest, p. 430 (1999).
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J. Eckhardt and P. D. Muench, 0.25 micron 1.8 V 1 GHz PLL for SOI Microprocessors, ISSCC Tech. Digest, p. 436 (1999).
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T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, Scaling Challenges and Device Design Requirements for High Performance Sub-50 nm Gate Length Planar CMOS Transistors, VLSI Tech. Digest, p. 174 (2000).
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Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, New York, 1998.
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J. W. Sleight, P. R. Varekamp, N. Lustig, J. Adkisson, A. Allen, O. Bula, X. Chen, T. Chou, W. Chu, J. Fitzsimmons, A. Gabor, S. Gates, P. Jamison, M. Khare, L. Lai, J. Lee, S. Narasimha, J. Ellis-Monaghan, K. Peterson, S. Rauch, S. Shukla, P. Smeys, T.-C. Su, J. Quinlan, A. Vayshenker, B. Ward, S. Womack, E. Barth, G. Biery, C. Davis, R. Ferguson, R. Goldblatt, E. Leobandung, J. Welser, I. Yang, and P. Agnello, A High Performance 0.13 µm SOI CMOS Technology with a 70 nm Silicon Film and with a Second Generation Low-k Cu BEOL, IEDM Tech. Digest, p. 245 (2001).
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C. J. Anderson, J. Petrovick, J. M. Keaty, J. Warnock, G. Nusbaum, J. M. Tendler, C. Carter, S. Chu, J. Clabes, J. DiLullo, P. Dudley, P. Harvey, B. Krauter, J. LeBlanc, P.-F. Lu, B. McCredie, G. Plum, P. J. Restle, S. Runyon, M. Scheuermann, S. Schmidt, J. Wagoner, R. Weiss, S. Weitzel, and B. Zoric, Physical Design of a Fourth-Generation POWER GHz Microprocessor, ISSCC Tech. Digest, p. 232 (2001).
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N. Zamdmer, A. Ray, J.-O. Plouchart, L. Wagner, N. Fong, K. A. Jenkins, W. Jin, P. Smeys, I. Yang, G. Shahidi, and F. Assaderaghi, SOI CMOS for Low Power and RF, Symposium on VLSI Technology, Digest of Technical Papers, 2001, p. 85.
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N. Zamdmer, J.-O. Plouchart, J. Kim, L.-H. Lu, S. Narasimha, A. Ray, M. Sherony, L. Wagner, N. Fong, and K. A. Jenkins, Networking Applications of a High-Performance 0.13-µm SOI CMOS Technology, Symposium on VLSI Technology, Digest of Technical Papers, 2002, in press.
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S. Narasimha, A. Ajmera, H. Park, D. Schepis, N. Zamdmer, K. A. Jenkins, J.-O. Plouchart, W.-H. Lee, J. Mezzapelle, J. Bruley, B. Doris, J. W. Sleight, S. K. Fung, S. H. Ku, A. C. Mocuta, I. Yang, P. V. Gilbert, K. P. Muller, P. Agnello, and J. Welser, High Performance Sub-40nm CMOS Devices on SOI for the 70nm Technology Node, IEDM Tech. Digest, p. 625 (2001).
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J. Cai, A. Ajmera, C. Ouyang, P. Oldiges, M. Steigerwalt, K. Stein, K. Jenkins, G. Shahidi, and T. Ning, Fully-Depleted-Collector Polysilicon-Emitter SiGe-Base Vertical Bipolar Transistor on SOI, Symposium on VLSI Technology, Digest of Technical Papers, 2002, in press.
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R. Hannon, S. S. K. Iyer, D. Sadana, J. P. Rice, H. L. Ho, B. A. Khan, and S. S. Iyer, 0.25 µm Merged Bulk DRAM and SOI Logic Using Patterned SOI, Symposium on VLSI Technology, Digest of Technical Papers, 2000, p. 66.
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H. L. Ho, M. D. Steigerwalt, B. L. Walsh, T. L. Doney, D. Wildrick, P. A. McFarland, J. Benedict, K. A. Bard, D. Pendleton, J. D. Lee, S. L. Maurer, B. Corrow, and D. K. Sadana, A 0.13 µm High-Performance SOI Logic Technology with Embedded DRAM for System-On-A-Chip Application, IEDM Tech. Digest, p. 503 (2001).
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