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IBM Journal of Research and Development  
Volume 46, Numbers 2/3, 2002
Scaling CMOS to the Limits
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SOI technology for the GHz era - Author bio

by G. G. Shahidi

Biographical sketch of author

G. G. Shahidi   IBM Microelectronics Division, East Fishkill facility, Route 52, Hopewell Junction, New York 12533 (shahidi@us.ibm.com). Dr. Shahidi received his B.S., M.S., and Ph.D. degrees, all in electrical engineering, from MIT. In 1989 he joined the IBM Thomas J. Watson Research Center, where he initiated the SOI development program. After demonstration of device design and 5-in. SOI material in the IBM Research Division, Dr. Shahidi, along with the SOI development effort, moved to the IBM Microelectronics Division Advanced Silicon Technology Center (ASTC) in Hopewell Junction, New York. Over the following years, Dr. Shahidi led the development of SOI CMOS technology at the ASTC. This work resulted in the development of 8-in. SOI technology infrastructure, demonstration of SOI performance gain, qualification of multiple CMOS SOI technologies and their transfer to manufacturing, establishment of design infrastructure, and the first mainstream use of SOI. Dr. Shahidi is currently the Director of High-Performance Logic Development, and an IBM Fellow.