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IBM Journal of Research and Development  
Volume 46, Numbers 2/3, 2002
Scaling CMOS to the Limits
 Table of contents: arrowHTML arrowPDF arrowASCII   This article: arrowHTML arrowPDF arrowASCII arrowCopyright info
   

Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? - References
by C. M. Osburn, I. Kim, S. K. Han, I. De, K. F. Yee, S. Gannavaram, S. J. Lee, C.-H. Lee, Z. J. Luo, W. Zhu, J. R. Hauser, D.-L. Kwong, G. Lucovsky, T. P. Ma, and M. C. Öztürk

References

  1. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of Ion Implanted MOSFET's with Very Small Physical Dimensions,” IEEE J. Solid-State Circuits SC-9, 256–268 (1974).
  2. J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, “Generalized Guide for MOSFET Miniaturization,” IEEE Electron Device Lett. 1, 2 (1980).
  3. International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2001; http://www.semichips.org.
  4. M. J. van Dort, P. H. Woerlee, and A. J. Walker, “A Simple Model for Quantization Effects in Heavily-Doped Silicon MOSFET's at Inversion Conditions,” Solid State Electron. 37, 411 (1994).
  5. S.-H. Lo, D. A. Buchanan, Y. Taur, L.-K. Han, and E. Wu, “Modeling and Characterization of n+ and p+ Polysilicon-Gated Ultra-Thin Oxides,” Symposium on VLSI Technology, Digest of Technical Papers, 1997, p. 149.
  6. S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET's,” IEEE Electron Device Lett. 18, 209–211 (1997).
  7. J. R. Hauser and K. Ahmed, “Characterization of Ultra-Thin Oxides Using Electrical C-V and I-V Measurement,” AIP Conference Proceedings, 1998, p. 235.
  8. C. A. Richter, A. R. Hefner, and E. M. Vogel, “A Comparison of Quantum-Mechanical Capacitance-Voltage Simulators,” IEEE Electron Device Lett. 22, 35–37 (2001).
  9. J. A. Lopez-Villanueva, I. Melchov, F. Gamiz, J. Banqueri, and J. A. Jimeneg-Tejoda, “A Model for the Quantized Accumulation Layer in Metal–Insulator-Semiconductor Structures,” Solid State Electron. 38, 203 (1995).
  10. C.-L. Huang and N. D. Arora, “Measurement and Modeling of MOSFET I-V Characteristics with Polysilicon Depletion Effect,” IEEE Trans. Electron Devices 40, 2330 (1993).
  11. S. Thompson, P. Packan, and M. Bohr, “MOS Scaling: Transistor Challenges for the 21st Century,” Intel Tech. J. 1, Third Quarter, 1998; www.Intel.com/technology/itj/q31998/pdf/trans.pdf.
  12. R. B. Fair, “Oxide Thickness Effect on Boron Diffusion in Thin Oxide P+ Si Gate Technology,” IEEE Electron Device Lett. 17, 242 (1996).
  13. M. V. Fischetti and S. E. Laux, “Long-Range Coulomb Interactions in Small Si Devices. Part I: Performance and Reliability,” J. Appl. Phys. 89, 1205 (2001).
  14. M. V. Fischetti, “Long-Range Coulomb Interactions in Small Si Devices. Part II: Effective Electron Mobility in Thin-Oxide Structures,” J. Appl. Phys. 89, 1232 (2001).
  15. V. Misra, G. Heuss, and H. Zhong, “Advanced Metal Electrodes for High-K Dielectrics,” Proceedings of the MRS Workshop, New Orleans, June 1–2, 2000, p. 5.
  16. I. De, D. Johri, A. Srivastava, and C. M. Osburn, “Impact of Gate Workfunction on Device Performance at the 50 nm Technology Node,” Solid State Electron. 44, 1077 (2000).
  17. H. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S.-I. Nakamure, M. Sitor, and H. Iwai, “Tunneling Gate Oxide Approach to Ultra-High Current Drive in Small-Geometry MOSFETs,” IEDM Tech. Digest, pp. 593–596 (1994).
  18. H. Iwai and H. Momose, “Ultra-Thin Gate Oxides—Performance and Reliability,” IEDM Tech. Digest, p. 163 (1998).
  19. H. S. Momose, S. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, “Uniformity and Reliability of 1.5 nm Direct Tunneling Gate Oxide MOSFETs,” Symposium on VLSI Technology, Digest of Technical Papers, 1997, pp. 15–16.
  20. H. S. Momose, S. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, “Study of the Manufacturing Feasibility of 1.5 nm Direct Tunneling Gate Oxide MOSFET's: Uniformity, Reliability, and Dopant Penetration of the Gate Oxide,” IEEE Trans. Electron Devices 45, 691 (1998).
  21. M. S. Krishnan, L. Chang, T.-J. King, J. Bokor, and C. Hu, “MOSFETs with 9 to 13Å Thick Gate Oxides,” IEDM Tech. Digest, pp. 241–244 (1999).
  22. I. Kim, S. K. Han, B. Keither, S. J. Lee, C. H. Lee, H. F. Luan, Z. Luo, E. Rying, Z. Wang, D. Wicaksana, H. Zhong, W. Zhu, J. Hauser, A. Kingon, D. L. Kwong, T. P. Ma, J. P. Maria, V. Misra, and C. M. Osburn, “Device Fabrication and Evaluation of Alternative High-K Dielectrics and Gate Electrodes Using a Non-Self Aligned Gate Process,” Proceedings of the Symposium on Rapid Thermal Processing, The Electrochemical Society, PV01-9, p. 211 (2001).
  23. R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, “30 nm Physical Gate Length CMOS Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays,” IEDM Tech. Digest, pp. 45–48 (2000).
  24. W.-K. Shih, C. M. Mazier, and A. F. Tasch, UTQUANT 2.0 User's Guide, University of Texas Press, Austin, October 1997.
  25. T. P. Ma, “Making Silicon Nitride a Viable Gate Dielectric,” IEEE Trans. Electron Devices 45, 680 (1998).
  26. H. Yang and G. Lucovsky, “Integration of Ultrathin (1.6~2.0 nm) RPECVD Oxynitride Gate Dielectrics into Dual Poly-Si Gate Submicron CMOSFETs,” IEDM Tech. Digest, pp. 245–248 (1999).
  27. A. Chin, C. C. Liao, C. H. Eu, W. J. Chen, and C. Tsai, “Device and Reliability of High-K Al2O3 Gate Dielectric with Good Mobility and Low Dit,” Symposium on VLSI Technology, Digest of Technical Papers, 1999, pp. 135–136.
  28. D. A. Buchanan, E. P. Gusev, E. Cartier, H. O. Schmidt, K. Rim, M. A. Gribelyuk, A. Mocutta, A. Ajmera, M. Copel, S. Guha, N. Bojarczuk, A. Callegari, C. D'Emic, P. Kozlowski, K. Chan, R. J. Fleming, O. C. Jamison, J. Brown, and R. Arndt, “80 nm Poly-Silicon Gated n-FET's with Ultra-Thin Al2O3 Gate Dielectrics for ULSI Applications,” IEDM Tech. Digest, pp. 223–226 (2000).
  29. K. J. Hubbard and D. G. Schlom, “Thermodynamic Stability of Binary Oxides in Contact with Silicon,” J. Mater. Res. 11, 2757 (1996).
  30. A. I. Kingon, J.-P. Maria, and S. K. Streiffer, “Alternative Dielectrics to Silicon Dioxide for Memory and Logic Devices,” Nature 406, 1032 (2000).
  31. G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k Gate Dielectrics: Current Status and Materials Properties Considerations,” Appl. Phys. Rev. 89, 5243 (2001).
  32. Y. Momiyama, H. Minakata, and T. Sugii, “Ultra-Thin Ta2O5/SiO2 Gate Insulator with TiN Gate Technology for 0.1 µm MOSFETs,” Symposium on VLSI Technology, Digest of Technical Papers, 1997, p. 135.
  33. J.-L. Autran, R. Devine, C. Chaneliere, and B. Balland, “Fabrication and Characterization of Si MOSFETs with PECVD Amorphous Ta2O5 Gate Insulator,” IEEE Electron Device Lett. 18, 447 (1997).
  34. I. C. Kiziyalli, P. K. Roy, F. Baumann, R. Y. Huang, D. Hwang, C. Chacon, R. Irwin, Y. Ma, and G. Alers, “Stacked Gate Dielectrics with TaO for Future CMOS Technologies,” Symposium on VLSI Technology, Digest of Technical Papers, 1998, p. 216.
  35. D. Park, Y.-C. King, Q. Lu, T.-J. King, C. Hu, A. Kalnitsky, S.-P. Tay, and C.-C. Cheng, “Transistor Characteristics with Ta2O5 Gate Dielectrics,” IEEE Electron Device Lett. 19, 441 (1998).
  36. H. F. Luan, B. Z. Wu, L. G. Kang, B. Y. Kim, R. Vrtis, D. Roberts, and D. L. Kwong, “Ultra Thin High Quality Ta2O5 Gate Dielectric Prepared by In-Situ Rapid Thermal Processing,” IEDM Tech. Digest, p. 609 (1998).
  37. H. F. Luan, S. J. Lee, C. H. Lee, S. C. Song, Y. L. Mao, Y. Senzaki, D. Robert, and D. L. Kwong, “High Quality Ta2O5 Gate Dielectrics with Tox,eq < 10Å,” IEDM Tech. Digest, pp. 141–144 (1999).
  38. G. B. Alers, D. J. Werder, Y. Chabal, H. C. Lu, E. P. Gusev, E. Garfunkel, T. Gustafsson, and R. S. Urdahl, “Intermixing at the Tantalum Oxide/Silicon Interface in Gate Dielectrics Structures,” Appl. Phys. Lett. 73, 1517 (1998).
  39. S. A. Campbell, D. C. Gilmer, X.-C. Wang, M.-T. Hsieh, H.-S. Kim, W. L. Gladfelter, and J. Yan, “MOSFET Transistors Fabricated with High Permittivity TiO2 Dielectrics,” IEEE Trans. Electron Devices 44, 104 (1997).
  40. X. Guo, T. P. Ma, T. Tamagawa, and B. L. Halpern, “High Quality Ultra-Thin TiO2/Si3N4 Gate Dielectric for Giga Scale MOS Technology,” IEDM Tech. Digest, p. 377 (1998).
  41. S. A. Campbell, R. Smith, N. Hoilien, B. He, and W. L. Gladfelter, “Group IVB Metal Oxides: TiO2, ZrO2, and HfO2 as High Permittivity Gate Insulators,” Proceedings of the MRS Workshop, New Orleans, June 1–2, 2000, p. 9.
  42. B. H. Lee, L. Kang, W.-J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee, “Ultra Thin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application,” IEDM Tech. Digest, pp. 133–136 (1999).
  43. S. J. Lee, H. F. Luan, C. H. Lee, T. S. Jeon, W. P. Bai, Y. Senaki, D. Roberts, and D. L. Kwong, “High Quality Ultra Thin CVD HfO2 Gate Stack with Poly-Si Gate Electrode,” IEDM Tech. Digest, pp. 31–34 (2000).
  44. B. H. Lee, L. Kang, R. Nieh, W.-J. Qi, and J. C. Lee, “Thermal Stability and Electrical Characteristics of Ultrathin Hafnium Oxide Gate Dielectric Reoxidized with Rapid Thermal Annealing,” Appl. Phys. Lett. 76, 1926 (2000).
  45. L. K. Kang, Y. Jeon, K. Onishi, B. H. Lee, W.-J. Qi, R. Nieh, S. Gopalan, and J. C. Lee, “Single-Layer Thin HfO2 Gate Dielectric with n+ Polysilicon Gate,” Symposium on VLSI Technology, Digest of Technical Papers, 2000, p. 44.
  46. Yanjun Ma, Yoshi Ono, Lisa Stecker, David R. Evans, and S. T. Hsu, “Zirconium Oxide Based Gate Dielectrics with EOT of Less Than 1.0 nm and Performance of Submicron MOSFET using a Nitride Gate Replacement Process,” IEDM Tech. Digest, p. 149 (1999).
  47. M. Copel, M. Gribelyuk, and E. Gusev, “Structure and Stability of Ultrathin Zirconium Oxide Layers on Si(001),” Appl. Phys. Lett. 76, 436 (2000).
  48. W.-J. Qi, R. Nieh, B. H. Lee, L. Kang, Y. Jeon, K. Onishi, T. Nagi, S. Banerjee, and J. C. Lee, “MOSCAP and MOSFET Characteristics Using ZrO2 Gate Dielectric Deposited Directly on Si,” IEDM Tech. Digest, p. 145 (1999).
  49. W.-J. Qi, R. Nieh, B. H. Lee, K. Onishi, L. Kang, Y. Jeon, J. C. Lee, V. Kaushik, B.-Y. Neuyen, L. Prabhu, K. Eisenbeiser, and J. Finder, “Performance of MOSFETs with Ultra Thin ZrO2 and Zr Silicate Gate Dielectrics,” Symposium on VLSI Technology, Digest of Technical Papers, 2000, p. 40.
  50. C. H. Lee, H. F. Luan, S. J. Lee, T. S. Jeon, W. P. Bai, Y. Sensaki, D. Roberts, and D. L. Kwong, “MOS Characteristics of Rapid Thermal CVD ZrO2 and Zr Silicate Gate Dielectrics,” IEDM Tech. Digest, p. 27 (2000).
  51. D. Wolfe, K. Flock, R. Therrien, R. Johnson, B. Raynor, L. Gunther, N. Brown, B. Claflin, and G. Lucovsky, “Remote Plasma-Enhanced Metal Organic Chemical Vapor Deposition of Zirconium Oxide/Silicon Oxide Alloy (ZrO2)x/(SiO2)1 – x (x less or = to 0.5) Thin Films for Advanced High-k Gate Dielectrics,” ULSI Gate Dielectrics, Mater. Res. Soc. Symp. Proc., pp. 343–348 (1999).
  52. T. Yamaguchi, H. Satake, N. Fukushima, and A. Toriumi, “Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-Silicate/Si MIS Structure Fabricated by Pulsed-Laser-Ablation Deposition,” IEDM Tech. Digest, pp. 19–22 (2000).
  53. M. Copel, M. Gribelyuk, and E. Gusev, “Structure and Stability of Ultrathin Zirconium Oxide Layers on Si(001),” Appl. Phys. Lett. 76, 436 (2000).
  54. G. D. Wilk and R. M. Wallace, “Electrical Properties of Hafnium Silicate Gate Dielectrics Deposited Directly on Silicon,” Appl. Phys. Lett. 74, 2854 (1998).
  55. G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and Zirconium Silicates for Advanced Gate Dielectrics,” J. Appl. Phys. 87, 484–492 (2000).
  56. G. D. Wilk and R. M. Wallace, “Stable Zirconium Silicate Gate Dielectrics Deposited Directly on Silicon,” Appl. Phys. Lett. 76, 436 (2000).
  57. W.-J. Qi, R. Nieh, E. Dharmarajan, B. H. Lee, Y. Jeon, L. Kang, K. Onishi, and J. C. Lee, “Ultrathin Zirconium Silicate Film with Good Thermal Stability for Alternative Gate Dielectric Application,” Appl. Phys. Lett. 77, 1704 (2000).
  58. A. Chin, Y. H. Wu, S. B. Chen, C. C. Lao, and W. J. Chen, “High Quality La2O3 and Al2O3 Gate Dielectrics with EOT 5~10Å,” Symposium on VLSI Technology, Digest of Technical Papers, 2000, pp. 16–17.
  59. Y. H. Wu, M. Y. Yang, and C. M. Kwei, “Electrical Characteristics of High Quality La2O3 Gate Dielectric with EOT of 5Å,” IEEE Electron Device Lett. 21, 7 (2000).
  60. S. Guha, E. Cartier, M. A. Gribelyuk, N. A. Bojarczuk, and M. C. Copel, “Atomic Beam Deposition of Lanthanum and Yttrium Based Oxide Thin Films for Gate Dielectrics,” Appl. Phys. Lett. 77, 2710 (2000).
  61. A. I. Kingon, J. P. Maria, D. Wicaksana, and J. Parrette, “Processing and Property Issues for the La2O3–SiO2 and HfO2–SiO2 Systems in Gate Stack Applications,” Proceedings of the MRS Workshop on High-k Gate Dielectrics, New Orleans, May 2000, pp. 31–32.
  62. L. Manchanda, M. L. Green, R. B. van Dover, M. D. Morris, A. Kerber, Y. Hu, J.-P. Han, P. J. Silverman, T. W. Sorsch, G. Weber, V. Donnelly, K. Pelhos, F. Klemens, N. A. Ciampa, A. Kornblit, Y. O. Kim, J. E. Bower, D. Barr, E. Ferry, D. Jacobson, J. Eng, B. Busch, and H. Schulte, “Si-Doped Aluminates for High Temperature Metal-Gate CMOS: Zr-Al-Si-O, A Novel Gate Dielectric for Low Power Applications,” IEDM Tech. Digest, pp. 23–26 (2000).
  63. S. Takagi, M. Iwase, and A. Toriumi, “On the Universality of Inversion-Layer Mobility in n- and p-Channel MOSFET's,” IEDM Tech. Digest, pp. 398–401 (1988).
  64. G. M. Yeric, A. F. Tasch, and S. K. Banerjee, “A Universal MOSFET Mobility Degradation Model for Circuit Simulation,” IEEE Trans. Computer-Aided Design 9, 1123 (1991).
  65. J. R. Hauser, “Extraction of Experimental Mobility Data for MOS Devices,” IEEE Trans. Electron Devices 43, 1981 (1996).
  66. J. Robertson, “Band Offsets of Wide-Band-Gap Oxides and Implications for Future Electronic Devices,” J. Vac. Sci. Technol. B 18, 1785–1791 (2000).
  67. G. Lucovsky, J. L. Whitten, and Y. Zhang, “A Molecular Orbital Model for the Electronic Structure of Transition Metal Atoms in Silicate and Aluminate Alloys,” Microelectron. Eng. 59, 329–334 (2001).
  68. K. K. Ng and W. T. Lynch, “The Impact of Intrinsic Series Resistance on MOSFET Scaling,” IEEE Trans. Electron Devices ED-34, 503–511 (1987).
  69. K. K. Ng and W. T. Lynch, “Analysis of Gate-Voltage Dependent Series Resistance of MOSFETs,” IEEE Trans. Electron Devices ED-33, 965–972 (1986).
  70. Y. Taur, C. H. Wann, and D. J. Frank, “25 nm CMOS Design Considerations,” IEDM Tech. Digest, pp. 789–792 (1998).
  71. H.-S. P. Wong, D. J. Frank, and P. Solomon, “Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFETs at the 25 nm Channel Length Generation,” IEDM Tech. Digest, p. 407 (1998).
  72. C. M. Osburn, I. De, K. F. Yee, and A. Srivastava, “Design and Integration Considerations for End-of-the-Roadmap Ultrashallow Junctions,” J. Vac. Sci. Technol. B 18, 338–345 (2000).
  73. K. Goto, M. Kase, Y. Momiyama, H. Kurata, T. Tanaka, M. Deura, Y. Sanbonsugi, and T. Sugii, “A Study of Ultra Shallow Junction and Tilted Channel Implantation for High Performance 0.1 µm pMOSFETs,” IEDM Tech. Digest, p. 631 (1998).
  74. Y. Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M. R. Wordeman, B. Davari, and G. G. Shahidi, “A New Shift and Ratio Method for MOSFET Channel Length Extraction,” IEEE Electron Device Lett. 13, 267–269 (1992).
  75. Y. Taur, Y.-J. Mii, R. Logan, and H.-S. Wong, “On 'Effective Channel Length' in 0.1-µm MOSFET's,” IEEE Electron Device Lett. 16, 136–138 (1995).
  76. S. Gannavaram and M. C. Öztürk, “Ultra-Shallow P+-N Junctions for 35–70 nm CMOS Using Selectively Deposited Very Heavily Boron Doped Silicon–Germanium Films,” Rapid Thermal and Other Short-Time Processing Technologies, The Electrochemical Society, PV 00-9, p. 73, 2000.
  77. S. Gannavaram, N. Pesovic, and M. C. Öztürk, “Low Temperature (lesser_or_equal 800°C) Recessed Junction Selective Silicon–Germanium Source/Drain Technology for Sub-70 nm CMOS,” IEDM Tech. Digest, pp. 437–440 (2000).
  78. S. Gannavaram and M. C. Öztürk, “Ultra-Shallow p+-n Junctions for Sub 30 nm CMOS Using Selectively-Deposited, Very Heavily Boron-Doped SiGe Films,” J. Electrochem. Soc. (2002).
  79. H. R. Huff, A. Agarwal, Y. Kim, L. Pennymore, D. Riley, J. Barnett, C. Sparks, M. Freiler, G. Gebara, B. Bowers, P. J. Chen, P. Lysaght, B. Nguyen, J. E. Lim, S. Lim, G. Bersuker, P. Zeitzoff, G. A. Brown, C. Young, B. Foran, F. Shaapur, A. Hou, C. Lim, H. AsShareef, S. Borthakur, D. J. Derro, R. Bergmann, L. A. Larson, M. I. Gardner, J. Gutt, R. W. Murto, K. Torres, and M. D. Jackson, “Integration of High-K Gate Stack Systems into Planar CMOS Process Flows,” Proceedings of the International Workshop on Gate Insulators, Tokyo, November 1–2, 2001, pp. 2–11.
  80. A. Chatterjee, R. A. Chapman, G. Dixit, and I. C. Chen, “Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by Replacement Gate Process,” IEDM Tech. Digest, p. 821 (1997).
  81. A. Chatterjee, R. A. Chapman, K. Joyner, M. Otobe, S. Hattangady, M. Bevan, G. A. Brown, H. Yang, Q. He, D. Rogers, S. J. Fang, R. Kraft, A. L. P. Rotondoro, M. Terry, K. Brennan, S.-W. Aur, J. C. Hu, K.-L. Tsai, P. Jones, G. Wilk, M. Aoki, M. Rodder, and I.-C. Chen, “CMOS Metal Replacement Gate Transistors Using Tantalum Pentoxide Gate Insulator,” IEDM Tech. Digest, p. 777 (1998).
  82. A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G. Minamihaba, H. Kano, K. Hieda, K. Suguro, T. Arikado, and K. Okumura, “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1 µm Regime,” IEDM Tech. Digest, pp. 785–788 (1998).
  83. A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, K. Matsuo, Y. Akasaka, Y. Ozawa, H. Yano, G. Minamihaba, Y. Matsui, Y. Tsunashima, K. Suguro, T. Arikado, and K. Okumura, “Reduction of Threshold Voltage Deviation in Damascene Metal Gate MOSFETs,” IEDM Tech. Digest, pp. 257–260 (1999).
  84. T. Matsuki, K. Kishimoto, K. Fujii, N. Itoh, K. Yoshida, K. Ohto, S. Yamasaki, T. Shinmura, and N. Kasai, “Cu/Poly-Si Damascene Gate Structured MOSFET with Ta and TaN Stacked Barrier,” IEDM Tech. Digest, pp. 261–264 (1999).
  85. Y. Ma, D. R. Evans, T. Nguyen, Y. Ono, and S. T. Hsu, “Fabrication and Characterization of Sub-Quarter Micron MOSFET's with a Copper Gate Electrode,” IEEE Electron Device Lett. 20, 254–255 (1999).
  86. A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, K. Hieda, Y. Tsunashima, K. Suguro, T. Arikado, and K. Okumura, “High Performance Damascene Metal Gate MOSFET's for 0.1 µm Regime,” IEEE Trans. Electron Devices 47, 1028–1034 (2000).
  87. See for example B. El-Kareh, Fundamentals of Semiconductor Process Technologies, Kluwer Academic Press, Boston, pp. 563–564, 1995.
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