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by E. J. Nowak |
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References
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International Technology Roadmap for Semiconductors, 1999 Edition, Semiconductor Industry Association, 4300 Stevens Suite Boulevard, Suite 271, San Jose, CA 95129.
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H. Ooka, S. Murakami, M. Murayama, K. Yoshida, S. Takao, and O. Kudoh, “High Speed CMOS Technology for ASIC Application,” IEDM Tech. Digest, pp. 240–243 (1986).
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S. Song, J. H. Yi, W. S. Kim, J. S. Lee, K. Fujihara, H. K. Kang, J. T. Moon, and M. Y. Lee, “CMOS Device Scaling Beyond 100 nm,” IEDM Tech. Digest, pp. 235–238 (2000).
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R. Dennard, F. Gaensslen, H. Yu, V. Rideout, E. Bassous, and A. LeBlanc, “Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,” IEEE J. Solid-State Circuits SC-9, 256–268 (1974).
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L. K. Han, S. Biesemans, J. Heidenreich, K. Houlihan, C. Lin, V. McGahay, T. Schimi, A. Schmidt, U. P. Schroeder, M. Stetter, C. Wann, D. Warner, R. Mankopf, and B. Chen, “A Modular 0.13µm Bulk CMOS Technology for High Performance and Low Power Applications,” IEEE Symposium on VLSI Technology, Digest of Technical Papers, 2000, pp. 12–13.
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C. H. Diaz, M. Chang, W. Chen, M. Chiang, H. Su, S. Chang, P. Lu, K. Pan, C. Yang, L. Chen, C. Su, C. Wu, C. H. Wang, C. C. Wang, J. Shih, H. Hsieh, H. Tao, S. Jang, M. Yu, S. Shue, B. Chen, T. Chang, C. Hou, B. K. Liew, K. H. Lee, and Y. C. Sun, “A 0.15 µm CMOS Foundry Technology with 0.1 µm Devices for High Performance Applications,” IEEE Symposium on VLSI Technology, Digest of Technical Papers, 2000, pp. 146–147.
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D. Pham, “Selective Device-Temperature Scaling for Optimum Performance–Power in MOSFET Circuit Design,” Ph.D. thesis, University of Vermont, Burlington, May 1998.
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K. Bernstein, J. Bertsch, L. Heller, E. Nowak, and F. White, “Experimental 2.0V Power/Performance Optimization of a 3.6V-Design CMOS Microprocessor-PowerPC 602,” IEEE Symposium on VLSI Technology, Digest of Technical Papers, 1994, pp. 83–84.
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D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized Scale Length for Two-Dimensional Effects in MOSFETs,” IEEE Electron Device Lett. 19, 385 (1998).
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J. B. Burr, “Cryogenic Ultra Low Power CMOS,” Proceedings of the IEEE Symposium on Low Power Electronics, 1995, pp. 82–83.
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G. Schrom, C. Pichler, T. Simlinger, and S. Selberherr, “On the Lower Bounds of CMOS Supply Voltage,” Solid State Electron. 39, 225–430 (1996).
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D. J. Frank, R. Dennard, E. J. Nowak, P. Solomon, Y. Taur, and H.-S. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies,” Proc. IEEE, pp. 259–288 (March 2001).
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A. Bryant, J. Brown, P. Cottrell, J. Ellis-Monaghan, M. Ketchen, and E. J. Nowak, “Low Power CMOS at Vdd = 4kT/q,” Conference Digest, 59th Device Research Conference, June 2001, pp. 22–23.
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A. Ajmera, J. W. Sleight, F. Assaderaghi, R. Bolam, A. Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, W. Rausch, D. Sadana, D. Schepis, L. F. Wagner, K. Wu, and B. Davari, “0.22 µm CMOS–SOI technology with a Cu BEOL,” IEEE Symposium on VLSI Technology, Digest of Technical Papers, 1999, pp. 15–16.
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K. Cox, J. Scott, S. Bishop, M. Bhat, B. Mettleton, D. Pan, M. Hamilton, D. Chang, L. Day, and P. Schani, “A Partially Depleted 1.8V SOI SRAM Technology Featuring a 3.77µm2 Cell,” IEEE Symposium on VLSI Technology, Digest of Technical Papers, 2000, pp. 13–15.
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K. Sukegawa, M. Yamaji, K. Yoshie, K. Furomochi, T. Maruyama, H. Morioka, N. Naori, T. Kubo, H. Kanata, M. Kai, S. Satoh, T. Izawa, and K. Kubota, “High-Performance 80-nm Gate Length SOI–CMOS Technology with Copper and Very-Low-k Interconnects,” IEEE Symposium on VLSI Technology, Digest of Technical Papers, 2000, pp. 186–187.
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M. Ino, H. Sawada, K. Nishimura, M. Urano, H. Sato, S. Date, T. Ishihara, T. Takeda, Y. Kado, H. Inokawa, T. Tsuchiya, Y. Sakakibara, Y. Arita, K. Izumi, K. Takeya, and T. Sakai, “.25µm CMOS/SIMOX Gate Array LSI,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1996, p. 86.
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R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, “30nm Physical Gate Length CMOS Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays,” IEDM Tech. Digest, pp. 45–48 (2000).
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S. Christoloveanu, T. Ernst, D. Munteanu, and T. Ouisse, “Ultimate MOSFETs on SOI: Ultra Thin, Single Gate, Double Gate, or Ground Plane,” Int. J. High Speed Electron. & Syst. 10, 217–230 (2000).
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X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub 50-nm FinFET,” IEDM Tech. Digest, pp. 67–70 (1999).
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D. M. Fried, A. P. Johnson, E. J. Nowak, J. Rankin, and C. R. Willets, “A sub-40 nm Body-Thickness N-type FinFET,” Conference Digest, 59th Device Research Conference, June 2001, pp. 24–25.
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D. Hisamoto, W.-C. Lee, J. Kedzierski, A. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, and C. Hu, “A Folded-Channel MOSFET for Deep-Sub-Tenth Micron Era,” IEDM Tech. Digest, pp. 1032–1034 (1998).
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D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, “A Fully Depleted Lean-Channel Transistor (DELTA),” IEDM Tech. Digest, pp. 833–836 (1989).
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J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. Willets, A. Johnson, S. Cole, H. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. Cottrell, M. Ieong, and P. Wong, “High-Performance Symmetric Gate and CMOS-Compatible Vt Asymmetric Gate FinFET Devices,” IEDM Tech. Digest, pp. 437–440 (2001).
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“Method for Making Submicron Dimensions in Structures Using Sidewall Image Transfer Techniques,” C. Johnson, S. Ogura, J. Riseman, N. Rovedo, and J. J. Shepard, IBM Tech. Disclosure Bull. 02-84, 4587–4589 (1984).
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“1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS,” M. Mutoh, T. Douskei, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, IEEE J. Solid-State Circuits 30, 847–854 (1995).
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