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by R. Nair |
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References
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C. J. Anderson, J. Petrovick, J. M. Keaty, J. Warnock, G. Nussbaum, J. M. Tendler, C. Carter, S. Chiu, J. Clabes, J. DiLullo, P. Dudley, P. Harvey, B. Krauter, J. LeBlanc, P.-F. Lu, B. McCredie, G. Plum, P. J. Restle, S. Runyon, M. Scheuermann, S. Schmidt, J. Wagoner, R. Weiss, S. Weitzel, and B. Zoric, Physical Design of a Fourth-Generation POWER GHz Microprocessor, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, February 2001, pp. 232233.
-
International Technology Roadmap for Semiconductors, 1999 Edition, Semiconductor Industry Association, 4300 Stevens Suite Blvd., Suite 271, San Jose, CA 95129.
-
D. Burger and J. R. Goodman, Billion-Transistor Architectures, Guest Editors' Introduction, Computer 30, No. 9, 4649 (September 1997).
-
Y. Patt, S. J. Patel, M. Evers, D. H. Friendly, and J. Stark, One Billion Transistors, One Uniprocessor, One Chip, Computer 30, No. 9, 5157 (September 1997).
-
M. H. Lipasti and J. P. Shen, Superspeculative Microarchitecture for Beyond AD 2000, Computer 30, No. 9, 5966 (September 1997).
-
J. E. Smith and S. Vajapayem, Trace Processors: Moving to Fourth-Generation Microarchitectures, Computer 30, No. 9, 6874 (September 1997).
-
K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang, The Case for a Single-Chip Multiprocessor, Proceedings of the Seventh International Symposium on Architectural Support for Parallel Languages and Operating Systems, October 1996, pp. 211.
-
G. Amdahl, Validity of the Single Processor Approach to Achieving Large-Scale Computing Capabilities, Proc. AFIPS 30, 483485 (1967).
-
R. Nair, Dynamic Path-Based Branch Correlation, Proceedings of the 28th Annual International Symposium on Microarchitecture, MICRO-28, November 1995, pp. 1523.
-
D. E. Lenoski and W.-D. Weber, Scalable Shared-Memory Multiprocessing, Morgan Kaufmann Publishers, San Francisco, CA, 1995.
-
E. Kronstadt, Some Observations Based on Simple Models of MP Scaling, Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, Austin, TX, April 2000, pp. 123128.
-
G. F. Pfister, In Search of Clusters, Prentice-Hall, Inc., Upper Saddle River, NJ, 1998.
-
J. M. Nick, B. B. Moore, J.-Y. Chung, and N. S. Bowen, S/390 Cluster Technology: Parallel Sysplex, IBM Syst. J. 36, No. 2, 172202 (1997).
-
J. von Neumann, First Draft of a Report on the EDVAC, University of Pennsylvania Report for the U.S. Army Ordnance Department, 1945.
-
W. D. Hillis, The Connection Machine, MIT Press, Cambridge, MA, 1985.
-
IBM Blue Gene team: F. Allen, G. Almasi, W. Andreoni, D. Beece, B. J. Berne, A. Bright, J. Brunheroto, C. Cascaval, J. Castanos, P. Coteus, P. Crumley, A. Curioni, M. Denneau, W. Donath, M. Eleftheriou, B. Fitch, B. Fleischer, C. J. Georgiou, R. Germain, M. Giampapa, D. Gresh, M. Gupta, R. Haring, H. Ho, P. Hochschild, S. Hummel, T. Jonas, D. Lieber, G. Martyna, K. Maturu, J. Moreira, D. Newns, M. Newton, R. Philhower, T. Picunko, J. Pitera, M. Pitman, R. Rand, A. Royyuru, V. Salapura, A. Sanomiya, R. Shah, Y. Sham, S. Singh, M. Snir, F. Suits, R. Swetz, W. C. Swope, N. Vishnumurthy, T. J. C. Ward, H. Warren, and R. Zhou, Blue Gene: A Vision for Protein Science Using a Petaflop Supercomputer, IBM Syst. J. 40, No. 2, 310327 (2001).
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S. J. Hong and R. Nair, Wire Routing MachinesNew Tools for VLSI Physical Design, Proc. IEEE, pp. 5765 (January 1983).
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R. Nair, S. J. Hong, S. Liles, and R. Villani, Global Wiring on a Wire-Routing Machine, Proceedings of the 19th Design Automation Conference, Las Vegas, NV, June 1982.
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K.-T. Chueng, S. Dey, M. Rogers, and K. Roy, Test Challenges for Deep Sub-Micron Technologies, Proceedings of the 37th Design Automation Conference, Los Angeles, CA, June 2000, pp. 142149.
-
R. Amerson, R. Carter, W. B. Culbertson, P. Kuekes, and G. Snider, TeramacConfigurable Custom Computing, Proceedings of the 1995 IEEE Symposium on FPGAs for Custom Computing Machines, April 1995, pp. 3238.
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PowerPC 405GP Embedded Processor; Product Brief,
http://www-3.ibm.com/chips/products/powerpc/chips/.
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IBM Blue Logic Core Program: ASIC Core Descriptions, http://www.chips.ibm.com/products/asics/products/cores/corelist.html.
-
R. Ho, K. W. Mai, and M. A. Horowitz, The Future of Wires, Proc. IEEE, pp. 490504 (April 2001).
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J. L. Bower and C. M. Christensen, Disruptive Technologies: Catching the Wave, Harvard Business Review, pp. 4353 (JanuaryFebruary 1995).
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