IBM Skip to main content
  Home     Products & services     Support & downloads     My account  
  Select a country  
Journals Home  
  Systems Journal  
Journal of Research
and Development
  ·  Current Issue  
  ·  Recent Issues  
  ·  Papers in Progress  
  ·  Search/Index  
  ·  Orders  
  ·  Description  
  ·  Patents  
  ·  Recent publications  
  ·  Author's Guide  
  Staff  
  Contact Us  
  Related links:  
     IBM Microelectronics  
     ITRS  
     IBM Research  
IBM Journal of Research and Development  
Volume 46, Numbers 2/3, 2002
Scaling CMOS to the Limits
 Table of contents: arrowHTML arrowPDF arrowASCII   This article: arrowHTML arrowPDF arrowASCII arrowCopyright info
   

Effect of increasing chip density on the evolution of computer architectures - Author bio

by R. Nair

Biographical sketch of author

Ravi Nair   IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (nair@us.ibm.com). Dr. Nair graduated from the University of Illinois with a Ph.D. degree in computer science in 1978; he has worked at the IBM Thomas J. Watson Research Center since then. He spent a sabbatical year at Princeton University in 1987–1988 and has also taught at Columbia University. Dr. Nair has worked in the areas of computer architecture, design automation, and testing, and has several publications, patents, and IBM awards in these areas. His current interests include processor microarchitecture, dynamic compilation, and virtual machine technology. Dr. Nair is a member of the IBM Academy of Technology and a Fellow of the IEEE.