IBM Skip to main content
  Home     Products & services     Support & downloads     My account  
  Select a country  
Journals Home  
  Systems Journal  
Journal of Research
and Development
  ·  Current Issue  
  ·  Recent Issues  
  ·  Papers in Progress  
  ·  Search/Index  
  ·  Orders  
  ·  Description  
  ·  Patents  
  ·  Recent publications  
  ·  Author's Guide  
  Staff  
  Contact Us  
  Related link:  
     IBM Microelectronics  
IBM Journal of Research and Development  
Volume 46, Numbers 2/3, 2002
Scaling CMOS to the Limits
 Table of contents: arrowHTML arrowPDF arrowASCII   This article: arrowHTML arrowPDF arrowASCII arrowCopyright info
   

New insights into carrier transport in n-MOSFETs - References

by A. Lochtefeld, I. J. Djomehri, G. Samudra, D. A. Antoniadis

References

  1. J. G. Ruch, “Electron Dynamics in Short-Channel Field-Effect Transistors,” IEEE Trans. Electron Devices ED-19, 652 (1972).
  2. S. Chou, D. Antoniadis, and H. Smith, “Observation of Electron Velocity Overshoot in Sub-100-nm-Channel MOSFETs in Si,” IEEE Electron Device Lett. EDL-6, 665 (1985).
  3. G. Shahidi, D. Antoniadis, and H. Smith, “Electron Velocity Overshoot at Room and Liquid Nitrogen Temperatures in Silicon Inversion Layers,” IEEE Electron Device Lett. 8, 94 (1988).
  4. G. A. Sai-Halasz, M. F. Wordeman, D. P. Kern, S. Rishton, and E. Gamin, “High Transconductance and Velocity Overshoot in nMOS Devices at 0.1 µm Gate-Length Level,” IEEE Electron Device Lett. 8, 464 (1988).
  5. H. Hu, J. Jacobs, L. Su, and D. Antoniadis, “A Study of Deep-Submicron MOSFET Scaling Based on Experiment and Simulation,” IEEE Trans. Electron Devices 42, 669 (1995).
  6. M. Lundstrom, “Scattering Theory of the Short Channel MOSFET,” IEDM Tech. Digest, p. 387 (1996).
  7. F. Assad, Z. Ren, S. Datta, M. Lundstrom, and P. Bendix, “Performance Limits of Silicon MOSFET's,” IEDM Tech. Digest, p. 547 (1999).
  8. S. Chou and D. Antoniadis, “Relationship Between Measured and Intrinsic Transconductance of FETs,” IEEE Trans. Electron Devices ED-34, 448 (1987).
  9. T. Mizuno and R. Ohba, “Experimental Study of Nonstationary Electron Transport in Sub-0.1 µm Metal-Oxide-Silicon Devices: Velocity Overshoot and Its Degradation Mechanism,” J. Appl. Phys. 82, 5235 (1997).
  10. Y. Taur, C. Wann, and D. Frank, “25 nm CMOS Design Considerations,” IEDM Tech. Digest, p. 789 (1998).
  11. Z. Lee, “A New Inverse-Modeling-Based Technique for Sub-100-nm MOSFET Characterization,” Doctoral Dissertation, Massachusetts Institute of Technology, Cambridge, November 1998.
  12. Z. Lee, M. McIlrath, and D. Antoniadis, “Two-Dimensional Doping Profile Characterization of MOSFETs by Inverse Modeling Using I–V Characteristics in the Subthreshold Region,” IEEE Trans. Electron Devices 46, 1640 (1999).
  13. A. Lochtefeld and D. Antoniadis, “On Experimental Determination of Carrier Velocity in Deeply Scaled NMOS: How Close to the Thermal Limit?,” IEEE Electron Device Lett. 22, 96-97 (2001).
  14. F. Assad, Z. Ren, D. Vasileska, S. Datta, and M. Lundstrom, “Modeling On-Currents for n-MOSFETs: Ultimate Limits vs. the NTRS,” Proceedings of the 1999 International Conference on Modeling and Simulation of Microsystems, San Juan, Puerto Rico, 1999, p. 388.
  15. S. Datta, F. Assad, and M. Lundstrom, “The Silicon MOSFET from a Transmission Viewpoint,” Superlatt. & Microstruct. 23, 771 (1998).
  16. M. Pinto, E. Sangiorgi, and J. Bude, “Silicon MOS Transconductance Scaling into the Overshoot Regime,” IEEE Electron Device Lett. 13, 375 (1993).
  17. T. Mizuno and R. Ohba, “Physical Limitations and Design for Sub-0.1µm MOS Devices: Carrier Velocity Overshoot and Performance Fluctuations,” Electron. & Commun. Jpn., Part 2, 81, 18 (1998).
  18. K. Rim, J. Hoyt, and J. Gibbons, “Fabrication and Analysis of Deep Submicron Strained-Si n-MOSFETs,” IEEE Trans. Electron Devices 47, 1406 (2000).
  19. M. Fischetti and S. Laux, “Performance Degradation of Small Silicon Devices Caused by Long-Range Coulomb Interactions,” Appl. Phys. Lett. 76, 2277 (2000).
  20. A. Sabnis and J. Clemens, “Characterization of the Electron Mobility in the Inverted <100> Si Surface,” IEDM Tech. Digest, p. 18 (1979).
  21. M. Liang, J. Choi, P. Ko, and C. Hu, “Inversion-Layer Capacitance and Mobility of Very Thin Gate-Oxide MOSFET's,” IEEE Trans. Electron Devices ED-33, 409 (1986).
  22. M. Sherony, L. Su, J. Chung, and D. Antoniadis, “SOI MOSFET Effective Channel Mobility,” IEEE Trans. Electron Devices 41, 276 (1994).
  23. C. Sah, T. Ning, and L. Tschopp, “The Scattering of Electrons by Surface Oxide Charges and by the Lattice Vibrations at the Si–SiO2 Interface,” Surf. Sci. 32, 561 (1972).
  24. S. Sun and J. Plummer, “Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces,” IEEE Trans. Electron Devices ED-27, 1497 (1980).
  25. T. Ando, A. Fowler, and F. Stern, “Electronic Properties of Two-Dimensional Systems,” Rev. Mod. Phys. 54, 437 (1982).
  26. D. Jeon and D. Burk, “MOSFET Electron Inversion Layer Mobilities—A Physically Based Semi-Empirical Model for a Wide Temperature Range,” IEEE Trans. Electron Devices 36, 1456 (1989).
  27. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the Universality of Inversion Layer Mobility in Si MOSFETs: Part I—Effects of Substrate Impurity Concentration,” IEEE Trans. Electron Devices 41, 2357 (1994).
  28. R. Pierret, Field Effect Devices, Addison-Wesley Publishing Co., Reading, MA, 1990.
  29. Y. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill Book Co., Inc., New York, 1987.
  30. D. A. Antoniadis, I. J. Djomehri, and A. Lochtefeld, “Electron Velocity in Sub-50-nm Channel MOSFETs,” Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2001, pp. 156, 161.
  31. Y. Kanada, “A Graphical Representation of the Piezoresistive Coefficients in Silicon,” IEEE Trans. Electron Devices ED-29, 64 (1982).
  32. A. Lochtefeld and D. Antoniadis, “Investigating the Relationship Between Electron Mobility and Velocity in Deeply Scaled NMOS via Mechanical Stress,” IEEE Electron Device Lett. 22, 591-593 (2001).
  33. H. Wong, D. Frank, and P. Solomon, “Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFET's at the 25 nm Channel Length Generation,” IEDM Tech. Digest, p. 407 (1998).
  34. R.-H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: From Bulk to SOI to Bulk,” IEEE Trans. Electron Devices 39, 1704 (1992).
  35. D. Esseni, M. Mastrapasqua, C. K. Celler, F. H. Baumann, C. Fiegna, L. Selmi, and E. Sangiorgi, “Low Field Mobility of Ultra-Thin SOI N- and P-MOSFETs: Measurements and Implications on the Performance of Ultra-Short MOSFETs,” IEDM Tech. Digest, p. 671 (2000).
  36. L. Chang, S. Tang, T. King, J. Bokor, and C. Hu, “Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs,” IEDM Tech. Digest, p. 719 (2000).