1. Introduction

The current drive capability of deeply scaled MOSFETs and, in particular, n-MOSFETs has been the subject of investigation since the late 1970s. First it was hypothesized that the effective carrier injection velocity from the source into the channel would reach the limit of the saturation velocity and remain there as longitudinal electric fields increased beyond the onset value for velocity saturation. However, theoretical work indicated that velocity overshoot can occur even in silicon [1], and indeed it is routinely seen in the high-field region near the drain in simulated devices using energy balance models or Monte Carlo. While it was understood that velocity overshoot near the drain would not help current drive, early experimental work [2, 3] claimed to observe velocity overshoot near the source, which of course would be beneficial. Velocity was extracted from the intrinsic saturation transconductance, g_mi, normalized to device width, W, and inversion capacitance per unit area, C’_ox, as g_mi/WC’_ox. A similar claim was made at the same time by Sai-Halasz et al. [4] by fitting the saturated velocity in a drift-diffusion simulator to match experimental device currents. For a period of time it appeared that with good channel doping engineering velocity overshoot near the source could become practical in deeply scaled devices, but subsequent experimental work [5] demonstrated that there is a constraint between g_mi /WC’_ox (velocity) and drain-induced barrier lowering (DIBL). Indeed, velocity thus extracted could exceed the saturated velocity, but only at very high values of DIBL, where the devices would not be usable. That work also demonstrated the superiority of halos in the velocity vs. DIBL performance criterion, but for usable DIBL values, effective electron velocities have remained stubbornly well below the saturation velocity.

In this paper we revisit the issue of effective injection velocity and its relation to effective mobility using a combination of experiments and simulation. Strictly speaking, effective mobility is commonly obtained vs. effective transverse electric field from long-channel device measurements and is assumed to be constant along the channel. However, in modern short-channel devices with strong doping halos, mobility is not expected to be constant along the channel, so, by effective mobility, we mean the average mobility in the channel. An additional difficulty in extending the mobility concept to very-short-channel devices comes from the fact that the halo doping dimensions, and indeed the channel length itself, are only moderately greater than the electron mean free path. Nevertheless, since it is found that at low longitudinal fields, irrespective of doping scheme or channel length, current and thus carrier velocity are proportional to field, an effective mobility can always be defined. We interpret this effective mobility as a quantity proportional to the average carrier scattering rate. It is shown here that effective mobility (at low longitudinal field) and velocity (at high field) are correlated and are both degraded as bulk n-MOSFETs are scaled down, probably because of increased surface and ionized impurity scattering. Alternative device structures that may overcome this limitation are then discussed briefly.

2. Effective channel-injection velocity in sub-100-nm n-MOSFETs

Continued success in scaling bulk MOSFETs has brought increasing focus on fundamental device performance limits. The ultimate limit to performance is thought to be the thermal injection velocity v (1.2–2 × 10⁷ cm/s) from the source accumulation layer into the channel [6, 7]. By applying the formalism of 1-flux scattering theory [6], the limit can be stated as

Ion/W = vQi(x0)T/(2 – T),

(1)

where I_on is the saturated drain current and Q_i(x₀) is the areal inversion layer density at the conduction-band peak at x = x₀ (with V_gs = V_ds = V_dd) at the source side of the channel. x denotes longitudinal channel position. The effective channel-injection carrier velocity at x₀ is

veff = vT/(2 – T).

(2)

T is the transmission coefficient at x₀; T = 1 (and v_eff = v) represents fully ballistic transport (i.e., no backscattering from the channel back to the source). As a measure of how close to the thermal limit a device operates, it is conceptually useful to define a thermal or ballistic efficiency, ß:

ß veff/v = T/(2 – T).

(3)

To estimate T and ß, v_eff must be determined experimentally (v can be estimated theoretically [7]) as close to the conduction-band peak as possible, if the goal is to assess how near to the ballistic limit a modern MOSFET operates. The answer to this question has important ramifications: Large ß for a modern “standard” MOSFET would suggest that only minor drive-current benefit could be expected from continued scaling, or from technology alternatives for mobility improvement (e.g., strained Si or undoped thin-film SOI), as we later discuss. In the following sections we discuss several experimental methods for estimating v_eff.

Carrier velocity from saturated transconductance
Effective carrier velocity can be measured from extrinsic or intrinsic saturated transconductance g_m and g_mi [3]:

vgm = gm/WC’ox,

(4)

vgmi  = gmi/WC’ox,

(5)

where C’_ox is the gate-oxide capacitance per unit area in inversion, g_mi is the saturated transconductance corrected for source/drain parasitic resistance (R_sd) as in [8], and W is the width of the device. v_gmi, corrected for R_sd, is a more accurate reflection of real channel carrier velocity than v_gm.

Carrier velocity from drain current and long-device CV
Conceptually, a more straightforward way to extract v_eff is to directly measure I_on/WQ_i(x₀). Determining Q_i(x₀) in deeply scaled devices is problematic because of uncertainties in channel length, large (relative) overlap and fringing capacitances, and nonuniform charge distribution along the channel. However, in strong inversion and in the gradual channel approximation, Q_i(x₀) in a short channel should correspond closely to the long-channel inversion layer charge
₀^V_gsC’_gsd|_Vds=0, where C’_gsd is the gate-to-source/drain (tied) capacitance, normalized to unit area. Choosing a device with a sufficiently long channel renders the fringing component of C’_gsd negligible. Accordingly, we let

Qi(x0)(short-chan.) =  Vgs*  C’gsd|Vds=0(long-chan.), 0

(6)

where V^*gs = V_gs + V_gs, with V_gs accounting for differences between long- and short-channel devices. The most important component in V_gs is V_t due to drain-induced barrier lowering (DIBL) and threshold-voltage rolloff. The expression for effective velocity as extracted from I_on becomes

vid = Ion/WQi(x0)(short-chan.) = Ion W  (Vgs+Vt) C’gsd(long-chan.) . 0

(7)

A second component in V_gs is due to voltage drop on the source resistance, I_onR_s. Adding this correction to the upper integration limit in Equation (7) gives the expression used for “intrinsic” effective velocity, v_idi:

vidi = Ion   W  (Vgs + Vt – IonRs) C’gsd(long-chan.)  . 0

(8)

Carrier velocity from drain current and short-device CV
A carrier velocity extraction technique was presented in [9] which we denote v_id2:

vid2 = Ion/WQi = Ion   W  Vgs C’gs(Vds = Vdd)  . Vt

(9)

C’_gs is the capacitance (per unit area) measured from the short device. Despite important advantages, this technique is difficult to apply to short-channel devices because of a significant fringing capacitance correction and the need to know L_eff accurately in order to normalize C’_gs. Even when accurately applied, this technique gives an average carrier velocity in the channel and not the velocity near x₀, as discussed below.

A simulated MOSFET was used to compare the different velocity-extraction methods. Each method was simulated exactly, and each extracted velocity was marked on the simulated velocity plot as x location, thus identifying the channel location for each technique. These are shown in Figure 1 for two different simulation models, drift-diffusion (DD) and energy balance (EB). The simulation results show clearly that the extraction methods developed in this work (v_id, v_idi) give inversion-layer carrier velocities closer to x₀ than the methods from the literature (v_gm, v_gmi, v_id2). However, v_id and v_idi also correspond to points in the channel somewhat beyond x₀. We must interpret, then, the subsequent experimental results (based on v_idi) as putting a reasonable upper bound on v_eff, and therefore ß, for the technologies investigated.

Figure 1

Experimental results
We measure v_id and v_idi (and compare with transconductance methods) for n-MOS devices from two advanced CMOS technologies, referred to in this work as technologies A and B (Table 1).¹ T_ox^elec was determined experimentally from _ox/C’_gsd (with V_gs = V_dd) measured in a large (L/W = 10 µm/10 µm) device. Source–drain parasitic series resistance values (R_sd) presented in Table 1 are estimated from inverse modeling [11, 12]. Some uncertainty in the technique is reflected by the presentation of a range of values for each technology. The use of these ranges on series resistances introduces negligible error for the relative comparisons between measured velocity for technology A vs. B. Absolute error in v_id and v_idi corresponding to this uncertainty in R_sd is at most 1.0–1.5%.

Table 1  Parameters for n-MOS technologies investigated.

Technology  Toxelec (nm) Vt (Vds = 50 mV, linear extrapolation, long chan.) (V) Nominal Vdd (V) Rsd (-µm) Leff for DIBL <130 mV/V (nm)   A 2.4 0.3 1.0 190–220 ~40 B 4.3 0.35 1.8 240–270 ~65

To determine Q_i(x₀) experimentally, we integrate C’_gsd obtained from a large (10-µm × 10-µm) device, and make adjustments according to Equation (6). C’_ox for v_gm and v_gmi was determined experimentally, from C’_gsd (V_gs = V_dd). The dependence of R_sd on gate bias is not taken into account because modest inaccuracies in R_sd do not significantly affect the results. Experimental results for technology A (Figure 2) [13] corroborate the simulation results, showing relative differences between v_id, v_idi, v_gm, and v_gmi of the same order. Similar results were found for the longer-channel technology B but with moderately less spread among the values. The fact that this difference is most pronounced at shorter channel lengths (either within one technology, or moving from B to A) suggests that with deeper scaling, effective velocity extraction via an I_on/WQ_i(x₀) method such as v_id or v_idi is increasingly necessary.

Figure 2

Effective velocity in comparison to ballistic limit
The thermal injection velocity is a function of channel doping and inversion-layer density [7], increasing with both. Our estimates for v are estimated from [7]. Using v = 1.7 × 10⁷ cm/s for technology A, and taking v_eff = v_idi from Figure 2, we find that for DIBL = 100 mV/V, ß = v_eff/v = 0.39, corresponding to an upper bound on T of 0.56. Table 2 summarizes experimental results for technologies A and B, as well as for 25-nm (L_eff) Monte Carlo simulation results from [10], all at the same DIBL of 100 mV/V. It is important to compare velocities of different technologies at equal DIBL (regardless of measurement technique), because for a given technology carrier velocity increases as electrostatic integrity decreases [5]. The experimental results suggest that ß is not increasing as we scale to shorter-channel-length generations. And, from the Monte Carlo results, it appears that with continued scaling (to 25 nm), bulk-Si n-MOS current drive would not be significantly above 40% of the thermally limited value. These results for technology B (ß = 0.47) are consistent with reported results² [14].

Table 2	Ballistic efficiency ß and transmission coefficient T. ß veff/v = T/(2 – T).

Properties 25-nm Monte Carlo Technology A Technology B   Veff (cm/s) 6.7–7.6 × 106 6.6 × 106 7.7 × 106 ß 0.35–0.40 0.39 0.47 T 0.52–0.57 0.56 0.64

In order to separate the effects of L_eff scaling from the corresponding changes in longitudinal electric field, the above experiments were repeated for different V_dd (= V_gs = V_ds). It is significant to note that, above V_dd = 1.0 V for technology A or 1.2 V for B, there is relatively little increase in carrier velocity with increasing drain bias. One possible explanation is the “tyranny of universal mobility,” whereby electrostatic integrity requires increasing transverse electric field, and therefore reduced mobility, as the channel length is scaled and the longitudinal field increased. Another explanation is offered by the scattering theory approach to estimating MOSFET drain current [6]. In this view, for a MOSFET in strong inversion and with high drain bias, I_on is only weakly dependent upon longitudinal field and therefore drain bias [15].

3. Mobility, scaling, and the low-field mobility–velocity relationship

Although longitudinal electric fields in the channel of a modern MOSFET are far in excess of the E_sat value that leads to velocity saturation, theoretical [6, 16] and experimental work [17, 18], as well as our own work described later in this paper, suggests that carrier velocity at or near x₀ still depends strongly on µ_eff in the sub-100-nm regime. We note, however, that there is no universal agreement about this strong correlation of carrier velocity with µ_eff, e.g. [19].

In bulk-Si and SOI MOSFETs, the effective low longitudinal field mobility, µ_eff (typically extracted from long-channel devices), behaves according to a “universal” relationship depending only on E_eff, the effective or average transverse field seen by carriers in the inversion layer [20–22]:

µ0 µeff =   ,  1 +     Eeff      E0

(10)

Eeff =  (Qi + Qb)  , si

(11)

where µ₀, E₀, , and are fitting parameters which depend on carrier type. = 1.6 and = 0.5 for electrons [21]. Q_i and Q_b are the inversion and channel depletion region charge areal densities, respectively. Typically for channel doping heavier than 2–3 × 10¹⁸ cm^–3, Q_b becomes the dominant contribution to E_eff.

Considering a wide range of temperature and transverse field conditions, the dominant scattering mechanisms for carriers in MOSFET inversion layers are Coulomb, phonon, and surface-roughness scattering [23–25]; we can therefore approximate by Matthiesson's rule [26]:

1  =  1  +  1  +  1  . µ µcoulomb µphonon µsr

(12)

In modern MOSFETs at room temperature, the “universal” mobility behavior is thought to be dominated by surface roughness and µ_sr µ_coulomb [27]. For deeply scaled MOSFETs, this may not be the case, and this issue is examined here with the help of measurements.

Experimental determination of low-field mobility
For small V_ds V_gs – V_t, it is well known that

Id = µeffC’ox   W   (Vgs – Vt)Vds, Leff

(13)

where L_eff is the effective channel length [28, 29]. As discussed in the Introduction, µ_eff for short-channel MOSFETs with strong halos should be considered (for small V_ds) as a proportionality ratio between electron velocity and longitudinal electric field, which at the long-channel limit becomes the well-defined lumped inversion charge mobility. Nevertheless, for either short or long devices, it is intimately related to carrier scattering rate, and as such it has meaning in either regime. Using the approximation Q_i C’_ox(V_gs – V_t), which is accurate in strong inversion, effective mobility can be determined according to

µeff =  IdLeff  , V *dsWQi

(14)

where Q_i is the low-V_ds inversion charge areal density obtained experimentally and assumed to be uniform throughout the channel. V^*_ds ( = V_ds – I_dR_sd) is the effective or intrinsic drain bias. For this investigation, both L_eff and R_sd are extracted from short-channel devices via inverse modeling [11, 12]. This, together with the determination of Q_i from Equation (6), allows Equation (14) to be used to determine mobility in short-channel devices.

We apply Equation (14) to measure the µ_eff vs. L_eff relationship for technology A. The long-channel devices obey the universal mobility relations quite well. To explore mobility behavior in short-channel devices for several values of constant inversion charge Q_i, we measure µ_eff via Equation (14) at three gate overdrives V_od = V_gs – V_t (where V_t is the linearly extrapolated value at V_ds = 50 mV). This is shown in Figure 3. Effective mobility at short channels appears to be independent of gate bias and inversion-charge density. This points toward strong Coulomb scattering at short channel lengths.

Figure 3

The mobility measured for two constant E_eff values is shown in Figure 4 [30]. This clearly demonstrates the disappearance of universal mobility behavior at short channels. This behavior, as well as the trend of µ_eff degradation (up to about 30% for the lower E_eff value), is interpreted as evidence that µ_coulomb < µ_sr. This is plausible because of the heavy source and drain halo dopings in the channels of these devices which merge for very short gate lengths. Therefore, device architectures that may allow undoped channels (see later) would be beneficial. On the other hand, the electron mobility may be suffering from long-range Coulomb interactions with electrons in the heavily doped source/drain and gate regions [19]. If that is the case, undoped channels would not yield a significant benefit.

Figure 4

The results of µ_eff versus channel length presented in this section should be considered preliminary for two reasons: sensitivity of experimental µ_eff to error in R_sd and L_eff estimations, and irregularities in asymptotic behavior of the results at longer channel lengths.

Electron velocity dependence on mobility in deep-sub-100-nm bulk n-MOS
The relation of low-field mobility to the performance of deep-sub-100-nm MOSFETs is still controversial. Here we investigate experimentally, for electrons in short (45-nm) n-MOS devices, the relation between mobility at low longitudinal electric fields (µ_eff) and velocity in the MOSFET saturation regime (v_eff), where peak longitudinal fields in the channel are high.

We investigate n-MOS transistors in the 1-V CMOS technology A, with L_eff for electrostatically sound devices (DIBL 120 mV/V) down to ~45 nm. Using a four-point bending apparatus, compressive and tensile uniaxial stress parallel to the direction of electron transport is applied to a silicon strip containing several processed dies. Surface strains of up to 0.12% are achieved. This method allows electrical characterization of the same set of devices with and without strain, reducing sources of experimental error. Fractional change in low-field effective mobility (µ_eff  µ_eff/µ_eff) corresponding to the induced strain is measured in long (10-µm) and short (45-nm) devices, as shown in Figure 5, using the technique described earlier. Some of the problems associated with mobility measurement in short devices—difficulty in accurately determining L_eff and Q_i [Equation (14)]—are not a significant problem for this experiment, because only the ratio of strained to unstrained mobility is required. When µ_eff-strained/µ_{eff-unstrained} is measured, the uncertainties in L_eff and Q_i cancel out. This “cancellation of uncertainties” does not apply to the drain-bias term. Determination of µ_eff in the long-channel device is not significantly affected by this. However, the sensitivity to R_sd is evident in the greater scatter among data points for
µ_eff-short: For each measurement at a new strain value, the probe-tip-to-pad contact resistance varies, slightly changing the total source/drain series resistance. This is also why the straight-line fit to the data does not pass through (0, 0) in Figure 5 for the short devices. The difference between µ_eff-long and µ_eff-short—a 40% reduction of dependence on strain for µ_eff in the short devices—may be indicative of a transition in the dominant scattering mechanism with device scaling, as discussed earlier, and is not unlike the Si piezoresistance coefficient reduction with increased doping [31].

Figure 5

Effective velocity versus mobility
Experimentally extracted v_gmi and v_idi are plotted against mobility shift for the short device in technology A, as shown in Figure 6 [32]. We denote the ratio v_e/µ_eff as R_vµ, and interpret it as a measure of the dependence of source-end electron velocity in the MOSFET saturation regime on low-field mobility. From Figure 6, R_vµ = 0.46 – 0.48. If this is calculated with long-channel mobility, R_vµ = 0.3, which is much lower. Clearly, for understanding transport in deep-sub-100-nm MOS devices, it is not valid to infer short-device mobility behavior from measurements of long devices from the same technology.

Figure 6

Earlier theoretical work with energy transport models [16] relating mobility to velocity agrees approximately, at the 50-nm-channel-length node, with our experimental results (R_vµ 0.5). We also performed 2D device simulations to support the measured results. Energy-balance (EB) modeling of a realistic simulated superhalo n-MOSFET with 2D doping profiles carefully designed to match measured subthreshold characteristics (DIBL, subthreshold slope, I_off) of the short (45-nm) devices with assumed change in the energy relaxation time _w = µ_eff (where _{w w}/_w), results in R_vµ = 0.55, reasonably close to the experimental value. This assumption of _w µ_eff has previously been used to successfully model Si/SiGe strained-Si MOSFETs [18].

If the piezoresistance effect in the source and drain resistance, R_sd, is accounted for with the help of a resistance test structure and inverse modeling, we find R_vµ is increased from 0.47 to 0.59 [32]. It is therefore reasonable to expect an R_vµ within the bounds of 0.45 and 0.60, which clearly indicates that increasing the low-field effective channel mobility continues to be beneficial even at L_eff = 45 nm.

4. Increased effective velocity in deeply scaled n-MOSFETs

From our observations, it appears that performance can improve if one can free the devices from the tyranny of Si universal mobility either by reducing E_eff while maintaining electrostatic integrity, or by shifting the whole mobility vs. E_eff curve up, as for example by use of biaxial strain (e.g., [18]). Since increased mobility leads to an increase in channel carrier velocity, the performance and ballistic efficiency will improve. Because a variety of options are being explored, and there are detailed papers on those in this issue, we discuss these options only briefly.

Step-doped bulk MOSFET
A hypothetical alternative to the nonuniformly doped channel is the perfect step-doped bulk MOSFET (also known as the ground-plane MOSFET [33, 34]), where channel doping, N_b = 0, down to depth T_step, and is arbitrarily high beyond. Maintaining other characteristics the same, E_eff is reduced in this structure, and hence mobility is enhanced over that of a uniformly doped bulk MOSFET, as shown in Figure 7. Note that in any doping scenario the E_eff near the source, where the mobility has its highest impact on velocity, is much reduced relative to mid-channel E_eff in a long device because of bulk charge-sharing with the source and also with the drain if the channel is short enough. Neglecting this 2D charge-sharing effect greatly overestimates the effect of channel doping on E_eff in short-channel devices. Therefore, the proper effective mobility can only be calculated from full 2D simulations. However, µ_eff is still much lower than in the case where there is no contribution to E_eff from the bulk charge. This limit is indicated by the dashed line without symbols in Figure 7. While there is no combination of channel and halo doping with gate work function that can reach this limit in scaled bulk devices, a potential alternative is the double-gate (DG) fully depleted SOI MOSFET, as discussed next.

Figure 7

Single- and double-gate fully depleted SOI MOSFET
The two alternatives for double-gate (DG) fully depleted SOI (FDSOI) design are illustrated schematically in Figure 8. Symmetrical DG–_mg (mg denotes mid-gap gate work function) has two inversion layers, while DG–n⁺p⁺ and single-gate (SG) FDSOI have one. In fully depleted SOI devices (Figure 8), short-channel effects are suppressed by limiting silicon and oxide film thicknesses. The deleterious effect of drain bias on source-side channel potential is limited by device geometry so that the requirement of the gradual channel is relaxed; FDSOI devices thus do not suffer as much from the “tyranny of universal mobility.” If alternative gate material processes can be developed such that gate work functions alone set an acceptable threshold voltage, Q_b can be essentially zero, and the µ_eff–E_eff range of operation is decoupled from device scaling. Figure 7 includes E_eff and µ_eff corresponding to the limits Q_b = 0 and _bi = 0, illustrating this potential benefit of reduced E_eff in FDSOI SG and DG MOSFETs as compared to bulk.

Figure 8

One might question the validity of using the bulk-Si µ_eff–E_eff curve for ultrathin-film SOI and DG–SOI devices. Provided the film is thicker than about 8 nm, as is the case for the devices considered here, it can be easily shown by the solution of coupled Poisson–Schrödinger equations that the presence of the second interface hardly modifies the inversion charge distribution of the first interface. Hence, the relationship between E_eff and the charge centroid distance from the interface is nearly the same as in bulk Si. In addition, recent experimental work with long-channel SOI devices with various Si film thicknesses [35] has shown that the bulk-Si universal mobility holds for film thicknesses down to about 9 nm.

For SG–_mg with Q_b Q_i, E_eff = Q_i/2_si. For DG–_mg, E_eff is further reduced by half, if Q_i is interpreted as the sum of inversion-layer charge at both gate interfaces: E_eff = Q_i/4_si. This indicates an important difference between transport in DG–_mg and DG–n⁺p⁺ devices. Since the latter has a single inversion layer (at the n⁺ interface for n-MOS), E_eff will be twice as high when compared with a DG–_mg device with the same total Q_i, resulting in a reduced µ_eff. Investigations have shown that DG FDSOI MOSFETs may ultimately scale to ~10 nm channel length [36]. For double-gate devices, our study indicates that hypothetical mid-gap top and bottom gates are superior to n⁺/p⁺ polysilicon gates in terms of both scalability and drive current.

The mobility-enhancement ranges achievable through these modified structures are summarized in Figure 9 at two different channel lengths of 50 and 25 nm. The advantages of the double-gate structure are very clear.

Figure 9

Biaxially strained Si-channel MOSFETs
The universal mobility limitations also can be overcome with the use of strained silicon on relaxed silicon– germanium by substantially shifting up the universal mobility curve. Biaxial strain raises electron mobility in n-MOSFETs much above the universal Si MOS curve. A mobility-enhancement ratio of ~1.75 at high transverse fields has been reported [18].

5. Conclusion

In summary, we have demonstrated a technique for measuring effective carrier velocity near the source side of the MOSFET channel which is more appropriate than existing techniques for the purpose of determining how close modern technologies are to the thermal (ballistic) limit. With this we have shown that a deeply scaled (L_eff < 50 nm) 1-V n-MOS technology operates, at most, at 40% of the limiting thermal velocity.

We have shown that mobility in the shortest n-MOSFETs from a deep-sub-100-nm technology does not behave according to a traditional universal relationship with E_eff. We interpret this as evidence that Coulomb scattering (perhaps from ionized channel impurities, but possibly from electrons in the source, drain, and gate regions) is limiting the mobility. Also, by corroborating measured velocity and mobility dependence on strain, we have demonstrated experimentally the importance of low-field effective inversion-layer mobility in deep-sub-100-nm bulk n-MOS in increasing the effective velocity. Thus, the ability of SG- and DG-FDSOI to maintain high mobilities with deep scaling over bulk becomes a very significant benefit. Hence, there are a variety of alternatives available to improve on ballistic efficiency by increasing effective mobility and, hence, effective channel velocity.

Acknowledgment

This work was supported by the DARPA AME Program and SRC grants.

References

Footnotes

¹ These devices were obtained courtesy of industrial partners.
² Mark Lundstrom, personal communication, March 2001.

Received June 5, 2001; accepted for publication October 24, 2001