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IBM Journal of Research and Development  
Volume 46, Numbers 2/3, 2002
Scaling CMOS to the Limits
 Table of contents: arrowHTML arrowPDF arrowASCII   This article: arrowHTML arrowPDF arrowASCII arrowCopyright info
   

Process modeling for future technologies - Author bio

by M. E. Law

Biographical sketch of author

Mark E. Law   Department of Electrical and Computer Engineering, University of Florida, P.O. Box 116130, Gainesville, Florida 32611 (law@tec.ufl.edu). Dr. Law is a Professor of Electrical and Computer Engineering and Co-Director of the SWAMP Center and of the Nanoscience and Technology Institute at the University of Florida. He received the B.S.Cpr.E. degree from Iowa State University in 1982, the M.S.E.E. degree from Stanford University in 1982, and the Ph.D. degree from Stanford University in 1988. He worked at Hewlett Packard from 1982 to 1985, joining the faculty at Florida in 1988. Dr. Law was named a National Science Foundation Presidential Faculty Fellow in 1992, Outstanding Young Alumni of Iowa State in 1994, College of Engineering Teacher of the Year in 1996–1997, and a UF Research Fellow in 1998. He is Editor-in-Chief of the IEEE Journal on Technology Computer-Aided Design, and has served as an editor of the IEEE Transactions on Semiconductor Manufacturing. He chaired the 1997 Simulation of Semiconductor Process and Devices Meeting, the 1999 silicon front-end processing symposium of the Materials Research Society, and the 2000 International Electron Devices Meeting. He has served on technical committees for several other conferences. Dr. Law has written more than 100 papers in the area of process and device modeling. He was named an IEEE Fellow in 1998 for his contributions to integrated-circuit process modeling and simulation.