IBM Skip to main content
  Home     Products & services     Support & downloads     My account  
  Select a country  
Journals Home  
  Systems Journal  
Journal of Research
and Development
  ·  Current Issue  
  ·  Recent Issues  
  ·  Papers in Progress  
  ·  Search/Index  
  ·  Orders  
  ·  Description  
  ·  Patents  
  ·  Recent publications  
  ·  Author's Guide  
  Staff  
  Contact Us  
  Related link:  
     IBM Microelectronics  
IBM Journal of Research and Development  
Volume 46, Numbers 2/3, 2002
Scaling CMOS to the Limits
 Table of contents: arrowHTML arrowPDF arrowASCII   This article: arrowHTML arrowPDF arrowASCII arrowCopyright info
   

Power-constrained CMOS scaling limits - References
by D. J. Frank

References

  1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies,” Proc. IEEE 89, 259–288 (2001).
  2. D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo Simulation of a 30 nm Dual-Gate MOSFET: How Far Can Si Go?,” IEDM Tech. Digest, p. 553 (1992).
  3. H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFETs at the 25 nm Channel Length Generation,” IEDM Tech. Digest, pp. 407–410 (1998).
  4. R. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: From Bulk to SOI to Bulk,” IEEE Trans. Electron Devices 39, 1704–1710 (1992).
  5. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,” IEEE J. Solid-State Circuits SC-9, 256–268 (1974).
  6. B. Davari, R. H. Dennard, and G. G. Shahidi, “CMOS Scaling, the Next Ten Years,” Proc. IEEE 89, 595–606 (1995).
  7. H.-S. P. Wong, D. J. Frank, P. M. Solomon, H.-J. Wann, and J. Welser, “Nanoscale CMOS,” Proc. IEEE 87, 537–570 (1999).
  8. D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized Scale Length for Two-Dimensional Effects in MOSFET's,” IEEE Electron Device Lett. 19, 385–387 (1998).
  9. S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET's,” IEEE Electron Device Lett. 18, 209 (1997).
  10. Y. Taur, C. H. Wann, and D. J. Frank, “25 nm CMOS Design Considerations,” IEDM Tech. Digest, pp. 789–792 (1998).
  11. R. B. Fair and H. W. Wivell, “Zener and Avalanche Breakdown in As-Implanted Low-Voltage Silicon N-P Junctions,” IEEE Trans. Electron Devices ED-23, 512 (1976).
  12. J. M. C. Stork and R. D. Isaac, “Tunneling in Base–Emitter Junctions,” IEEE Trans. Electron Devices ED-30, 1527 (1983).
  13. H. Kawaura, T. Sakamoto, and T. Baba, “Direct Source–Drain Tunneling Current in Subthreshold Region of Sub-10-Gate EJ-MOSFETs,” Si Nanoelectronics Workshop Abstracts, 1999, pp. 26–27.
  14. Y. Naveh and K. K. Likharev, “Modeling of 10-nm-Scale Ballistic MOSFETs,” IEEE Electron Device Lett. 21, 242–244 (2000).
  15. H.-S. Wong and Y. Taur, “Three-Dimensional 'Atomistic' Simulation of Discrete Microscopic Random Dopant Distributions Effects in Sub-0.1 µm MOSFETs,” IEDM Tech. Digest, pp. 705–708 (1993).
  16. H.-S. P. Wong, Y. Taur, and D. Frank, “Discrete Random Dopant Distribution Effects in Nanometer-Scale MOSFETs,” Microelectron. Reliability 38, 1447–1456 (1998).
  17. D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, “Monte Carlo Modeling of Threshold Variation Due to Dopant Fluctuations,” Symposium on VLSI Technology, Digest of Technical Papers, 1999, pp. 169–170.
  18. A. Asenov and S. Saini, “Random Dopant Fluctuation Resistant Decanano MOSFET Architectures,” Si Nanoelectronics Workshop Abstracts, 1999, pp. 84–85.
  19. E. Buturla, J. Johnson, S. Furkay, and P. Cottrell, “A New 3-D Device Simulation Formulation,” NASCODE VI: Sixth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits, Boole Press, Dublin, 1989, p. 291.
  20. D. J. Frank and H.-S. P. Wong, “Simulation of Stochastic Doping Effects in Si MOSFETs,” Proceedings of the International Workshop on Computational Electronics, 2000, pp. 2–3.
  21. D. Liu and C. Svensson, “Trading Speed for Low Power by Choice of Supply and Threshold Voltages,” IEEE J. Solid-State Circuits 28, 10 (1993).
  22. Z. Chen, J. Burr, J. Shott, and J. D. Plummer, “Optimization of Quarter Micron MOSFETs for Low Voltage/Low Power Applications,” IEDM Tech. Digest, pp. 63–65 (1995).
  23. D. J. Frank, P. Solomon, S. Reynolds, and J. Shin, “Supply and Threshold Voltage Optimization for Low Power Design,” Proceedings of the International Symposium on Low Power Electronics and Design, 1997, pp. 317–322.
  24. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Boker, and C. Hu, “Sub-20nm CMOS FinFET Technologies,” IEDM Tech. Digest, p. 421 (2001).
  25. D. B. Tuckerman and R. F. W. Pease, “High-Performance Heat Sinking for VLSI,” IEEE Electron Device Lett. 2, 126–129 (1981).
About IBM | Privacy | Legal | Contact