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IBM Journal of Research and Development  
Volume 46, Numbers 2/3, 2002
Scaling CMOS to the Limits
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Power-constrained CMOS scaling limits - Author bio

by D. J. Frank

Biographical sketch of author

David J. Frank   IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (djf@us.ibm.com). Dr. Frank received a B.S. degree from the California Institute of Technology, Pasadena, in 1977 and a Ph.D. degree in physics from Harvard University in 1983. Since graduation he has worked at the IBM Thomas J. Watson Research Center, where he is a Research Staff Member. His studies have included non-equilibrium superconductivity, modeling and measuring III–V devices, and exploring the limits of scaling of silicon technology. His recent work includes the modeling of innovative Si devices, analysis of CMOS scaling issues such as discrete dopant effects and short-channel effects associated with high-k gate insulators, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and low-power circuit design. Dr. Frank is a member of the IEEE; he has served on technical program committees for the International Electron Devices Meeting and the Si Nanoelectronics Workshop. He has authored or co-authored more than 70 technical publications and holds six U.S. patents.