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IBM Journal of Research and Development  
Volume 46, Numbers 2/3, 2002
Scaling CMOS to the Limits
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Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation - Author bio

by P. D. Agnello

Biographical sketch of author

Paul D. Agnello   IBM Research Division, Semiconductor Research and Development Center, Hopewell Junction, New York 12533 (agnellop@us.ibm.com). Dr. Agnello received his B.S., M.S., and Ph.D. degrees, all from the Electrical, Computer and Systems Engineering Department of Rensselaer Polytechnic Institute. He joined the IBM Thomas J. Watson Research Center in 1988. Dr. Agnello has received IBM Outstanding Technical Achievement Awards for low-temperature CVD processing and alloy silicide development. In addition, he has received an IBM Outstanding Innovation Award for the development of 0.25-µm CMOS technology and a Corporate Award for high-performance CMOS logic development. Recently he led the development of 0.18-µm-generation Cu back-end-of-line for high-performance CMOS; he currently manages the high-performance CMOS integration project responsible for 0.13-µm and beyond silicon-on-insulator technologies. Dr. Agnello is the author or co-author of more than 60 publications; he holds 15 U.S. patents.