Biographical sketches of authors

John M. Ludden   IBM Server Group, Burlington facility, Essex Junction, Vermont 05451 (ludden@us.ibm.com). Mr. Ludden is currently a Senior Engineer; he has been involved in design verification since joining IBM in 1990 after receiving a B.S. degree in electrical engineering from Rochester Institute of Technology. Mr. Ludden initially was involved in the verification of I/O and storage control subsystems for IBM S/390 mainframes. Since 1993, he has developed an expertise in the area of microprocessor verification, having leadership experience in the application of pseudorandom test-case generation as it applies to superscalar, out-of-order microprocessors. In particular, Mr. Ludden has applied such techniques to an x86 and several PowerPC microprocessors, including the POWER3 and POWER4. He has worked closely with the IBM Haifa Research Laboratory in Israel for more than eight years to improve test-generation capabilities in order to verify complex uniprocessor and multiprocessor design features. Mr. Ludden has received several informal recognition awards for his work on mainframes, microprocessors, RS/6000 workstations, servers, and SP supercomputers. He is actively involved in the IBM verification advisory team (VAT) and has been responsible for reviewing the verification plans for several other microprocessor designs within IBM in recent years.

Wolfgang Roesner   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (wolfgang@us.ibm.com). Dr. Roesner is an IBM Distinguished Engineer; he is the technical leader for Server Group verification tools development. He received the degrees of Dipl.-Ing. and Dr.-Ing. at the University of Kaiserslautern in 1980 and 1983. Dr. Roesner developed simulators and hardware design languages at IBM in Boeblingen, Germany, later joining the POWER processor development team, where he co-developed the TexSim simulation system. His verification tools have been used on all IBM CMOS microprocessor projects, and since 1996 he has been responsible for the strategy of verification tools development. Dr. Roesner has received three IBM Outstanding Achievement Awards and one IBM Corporate Award for development in hardware design language processing and simulation.

Gerry M. Heiling   8113 Asherton Cove, Austin, Texas 78750 (gheiling@swbell.net). Mr. Heiling received his B.S.E.E. degree from the University of Minnesota in 1967. He was employed at the Space Physics Division of Boeing from 1967 to 1969. In 1970, he received his M.S.E.E. degree from the University of Minnesota. That same year, Mr. Heiling joined IBM at Rochester, Minnesota, where he worked as an analog/digital circuit design engineer on a number of IBM products including System/3, System/36, System/38, and AS/400. From 1983 to 2001 he held various IBM management positions. He and his teams designed various analog, digital, and mixed-signal chips used in I/O, communication, and memory controller applications for IBM AS/400 and RS/6000 products. From 1996 to 2001, Mr. Heiling was a design manager in the RS/6000 processor group working on memory controllers/subsystems, L3 memory caches, and I/O controllers. He also managed the pre-silicon verification of the memory cache, I/O, and fabric portion of the POWER4 chip. Mr. Heiling holds ten patents with IBM. He is retired from IBM and resides in Austin, Texas.

John R. Reysa   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (reysa@us.ibm.com). Mr. Reysa joined IBM in 1987. He holds a B.S. degree in electrical engineering from Texas A&M University and an M.S. degree in electrical engineering from the University of Texas at Austin. He is a Senior Engineer in the POWER4 simulation group. Before assuming his current position, he managed the POWER3-II processor development effort. Prior to that, he managed the POWER3 simulation group, all in Austin, Texas. Mr. Reysa has received an IBM Outstanding Innovation Award for his work on RS/6000 simulation.

Jonathan R. Jackson   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (jrj1@us.ibm.com). Mr. Jackson is currently an Engineer in the IBM Server Group. He joined IBM in 2000. He received a B.E. degree with a double major in electrical engineering and computer science from Vanderbilt University in 1998 and an M.S. degree in electrical and computer engineering from Carnegie Mellon University in 2000. He currently works on storage subsystem verification for POWER4.

Bing-Lun Chu   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (bchu@us.ibm.com). Mr. Chu received his B.S. degree in engineering science from the State University of New York at Stony Brook in 1973 and his M.S. degree in electrical engineering from Cornell University in 1974. He joined IBM at Poughkeepsie in 1978, working on storage subsystem design for System/370. Later, he focused on SMP storage subsystem functional verification. Mr. Chu pioneered the use of a random driven/concurrent checking methodology that was proven to be extremely successful in several IBM products including the POWER4 storage subsystem, the zSeries server, and its predecessors. He is currently the team leader for POWER4 and its follow-on storage subsystem verification.

Michael L. Behm   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (mbehm@us.ibm.com). Mr. Behm is currently a Senior Engineer; he joined IBM in 1978. He received a A.S. degree in electronics technology from Lincoln Technical Institute in Allentown, Pennsylvania. He has spent five years in manufacturing test, three in the S/370 engineering laboratory, eight in S/390 core/vector processor verification, and the past seven years in POWER3/POWER4 core/chip verification. Mr. Behm's current assignment is core/chip architectual and u-architectual coverage verification.

Jason R. Baumgartner   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (jasonb@austin.ibm.com). Mr. Baumgartner joined IBM at Austin in 1995. He has spent most of his career as a development engineer in verification tool groups, currently working in functional formal verification (FFV) application/research/development. In addition to involvement in tool development, he is the technical leader of FFV deployment within the Austin Server Group. He has authored publications on several key new FV technologies, each of which has shown great utility in reducing FV complexity for industrial designs. Mr. Baumgartner received his B.S.E.E. degree from the University of Florida in 1995 and his M.S.C.E. degree from the University of Texas at Austin in 1998. He will be completing a Ph.D. in computer engineering from the University of Texas at Austin in 2002. He holds numerous patents in the area of FV, and has reached the Fifth IBM Invention Plateau.

Richard D. Peterson   IBM Server Group, 3605 Highway 52 North, Rochester, Minnesota 55901 (petersn@us.ibm.com). Mr. Peterson joined IBM in 1983; he is currently a Senior Engineer. Since 1992, he has been working on processor and system verification for IBM eServer, iSeries, and pSeries machines. Mr. Peterson received a B.S. degree in electrical engineering from the University of Texas in 1982, and an M.S. degree in computer engineering from the National Technological University in 1996. In 2001, he received an IBM Division Award for his contributions to AS/400 CEC verification.

Jamee Abdulhafiz   IBM Microelectronics Division, 11400 Burnet Road, Austin, Texas 78758 (abduljj@us.ibm.com). Mr. Abdulhafiz is currently a Senior Engineer and verification leader for a POWER4 derivative microprocessor. He has worked in verification since 1995 and was system verification team leader in the Enterprise Server Group. His previous experience included logic design from 1986 to 1994. Mr. Abdulhafiz received a B.S. and an M.S. degree in electrical and electronic engineering from the University of California at Los Angeles in 1986. He received an IBM Outstanding Technical Achievement Award for his work in RS/6000 MP verification in 1998 and an IBM Invention Achievement Award for his high-speed data access system patent submission in 1991.

William E. Bucy   IBM Server Group, 11400 Burnet Road, Austin Texas 78758 (bucy@us.ibm.com). Dr. Bucy joined IBM in New York in 1977, working in the Mid-Hudson Valley facilities from 1977 until 1991 as a Quality Assurance Engineer/Manager in the fields of semiconductor components, printed circuit cards and boards, and subassemblies. In 1985 he moved into development and contributed to the success of the IBM 200Mb Fiber Channel for data communication. In 1991, Dr. Bucy moved to IBM Austin, where he helped establish the system verification team for the RISC microprocessors. His most recent management accomplishments were in the functional system simulation of POWER3 and POWER4 products. Dr. Bucy received his B.S. degree in chemistry from West Virginia University in 1972 and his Ph.D in chemistry from the University of South Carolina in 1976. He is a member of Phi Beta Kappa.

John H. Klaus   IBM Server Group, 3605 Highway 52 North, Rochester, Minnesota 55901 (klaus@us.ibm.com). Mr. Klaus is currently a Senior Engineer; he joined IBM in 1981. He received a B.S. degree in electrical engineering from the Illinois Institute of Technology in 1981, and a master's degree in computer engineering from the University of Minnesota in 2000. Mr. Klaus has worked on the development of S/390 channels and I/O subsystems for 13 years; for the past six years he has been responsible for the hardware design verification of I/O chips on the AS/RS systems. He received an IBM Team Award for his work on the S/390 Parallel Sysplex Team and an IBM Excellence Award for his work on the Condor series of AS/RS machines.

Danny J. Klema   IBM Server Group, 3605 Highway 52 North, Rochester, Minnesota 55901 (klema@us.ibm.com). Mr. Klema is an Advisory Engineer in the System Pervasive Verification group. Before assuming his current position, he was team leader for printer attachment verification for AS/400 systems. He has also designed seveal chips and cards used in communications and I/O attachment for the S/36 and AS/400 systems. Mr. Klema received an IBM Excellence Award for his work in system verification for the Condor products. He has spent his entire career at IBM in Rochester, Minnesota, joining IBM in 1982. He holds a B.S. degree in electrical engineering from the University of North Dakota.

Tien N. Le   IBM Microelectronics Division, 11400 Burnet Road, Austin, Texas 78758 (tnle@us.ibm.com). Mr. Le received a B.S. degree in electrical engineering and a B.S degree in mathematics from California State Polytechnic University in 1974. In 1976, he received a B.S. degree in computer science and an M.S. degree in mathematics from the same institution. Mr. Le joined the IBM Office Products Division, working on system verification, printer designs, and manufacturing automation. In 1987 he joined the RS/6000 processor group, working on memory controllers/subsystems, caches, and I/O controllers. He pioneered a test-case-generating expert system that won a KBS Excellence Finalist Award in 1992. Mr. Le received a multiple-instance object creation patent in 1994 and three IBM Invention Achievement Awards. He is currently a technical team manager responsible for verifying the memory flow controller portion of the Sony–Toshiba–IBM joint-venture-designed processor in Austin, Texas.

F. Danette Lewis   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (danettel@us.ibm.com). Ms. Lewis is an Advisory Hardware Engineer in the POWER4 pervasive verification group. Before assuming her current position, she was a key member of the POWER4 fixed-point unit verification team; prior to that, she did PCI verification. Ms. Lewis has spent her entire career at IBM in Austin, Texas, joining IBM in 1980. She holds a B.S. degree in electrical engineering from New Mexico State University.

Philip E. Milling   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (pmilling@us.ibm.com). Mr. Milling is currently a Senior Engineer; he joined IBM in 1977. He received a B.S. degree in electrical engineering from the University of South Alabama in 1975 and an M.S. degree in electrical engineering from Colorado State University in 1980. Mr. Milling worked on the team which developed the IBM Personal Computer in Boca Raton, Florida, in 1981. In 1994, Mr. Milling moved to Austin, Texas, to support development of new RS/6000 PowerPC-based systems. Since 1997, Mr. Milling has worked primarily in system simulation, most recently supporting verification of POWER4-based systems. He has 24 invention disclosures published and holds six patents. Mr. Milling has received seven formal awards from IBM for his work on the IBM Personal Computer, the IBM POWER Personal Computer, and POWER4 systems.

Lawrence A. McConville   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (mccon@us.ibm.com). Mr. McConville is currently a Staff Engineer; he joined IBM in 1992 and worked in hardware qualification prior to joining system simulation in 1996. He received a B.S. degree in electrical engineering in 1990 and an M.S. degree in electrical engineering in 1991, both from the University of Nebraska at Lincoln. Most recently, he received an IBM Excellence Award for his work on the Condor series of AS/RS machines.

Bradley S. Nelson   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (bsnelson@us.ibm.com). Mr. Nelson received his B.S. degree in computer engineering from Texas A&M University in 1997. After graduation he joined the RS/6000 processor memory subsystem group. He worked as a verification team leader for the POWER4 memory controller and L3 data cache. During that time, he has pioneered new methodologies to verify asynchronous interfaces. He is now working as a verification project manager for the POWER5 memory subsystem design.

Viresh Paruthi   IBM Enterprise Systems Group, 11400 Burnet Road, Austin, Texas 78758 (vparuthi@us.ibm.com). Mr. Paruthi received the B.Tech.(H) degree in computer science and engineering from the Indian Institute of Technology, Kharagpur, in 1995, and an M.S. degree in computer engineering from the University of Cincinnati in 1997. He then joined the IBM Server Group, where he supported and applied the Verity Boolean equivalence checker to the POWER4 processor project. Later he assumed a development role, contributing to the development and enhancement of Verity's core algorithms. His current interests include functional formal and semiformal verification and abstractions in addition to Boolean equivalence checking. Mr. Paruthi has published numerous conference papers in the area of formal verification.

Travis W. Pouarz   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (tpouarz@us.ibm.com). Receiving a B.S. degree in electrical engineering from Duke University in 1998, Mr. Pouarz joined the IBM Server Group in Austin, Texas, to work on the development and application of Verity formal Boolean equivalence checking for the POWER4. He continues this work for the POWER4 successors and a number of other IBM high-performance microprocessors, as well as development for future formal verification tools. He is the company's Verity expert for high-performance full-custom circuitry and rigorous hierarchical methodology.

Audrey D. Romonosky   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (romonosk@us.ibm.com). Ms. Romonosky is currently a Senior Engineer; she joined IBM in 1978. She received a B.S. degree in electrical engineering from Pennsylvania State University in 1978 and an M.S. degree in computer engineering from Syracuse University in 1985. Ms. Romonosky worked on the logic development of S/390 and ES/9000 for 14 years and in Server Group system development since 1993. She has worked in system verification since 1996 on POWER3- and POWER4-based systems. Most recently, she received an IBM Excellence Award for her work on the POWER3 Nighthawk system.

Jeff Stuecheli   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (jeffas@us.ibm.com). Mr. Stuecheli has worked in the IBM Server Development Group in Austin since 1995. He received his B.S. degree in computer engineering from the University of Texas in 1997. He is currently enrolled in the Ph.D. program at UT Austin, researching computer architecture. His work at IBM includes system, RAS, storage subsystem, and, most recently, performance verification. Mr. Stuecheli has filed patents in both verification techniques and storage subsystem architecture.

Kent D. Thompson   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (kentthom@us.ibm.com). Mr. Thompson is a Staff Software Engineer in the POWER4 pervasive verification group. Before assuming his current position, he was a key member of the development team for the Engineering Support Processor. This tool was used for bringup and verification of all previous POWER and PowerPC chips. Mr. Thompson has spent his entire career at IBM in Austin, Texas, joining IBM in 1982. He holds a B.S. degree in computer science from St. Edwards University.

Dave W. Victor   IBM Server Group, 11400 Burnet Road, Austin, Texas 78758 (dvictor@us.ibm.com). Mr. Victor is currently a Senior Engineering Manager in charge of i/p series processor verification. He received his B.S. degree in electrical engineering and applied physics from Case Western Reserve University in 1988 and his M.S. degree in electrical engineering from Syracuse University in 1990. He joined IBM in 1988 as a chip designer for zSeries machines in Poughkeepsie, New York. Since then, he has been a logic designer and microarchitect on various processor, memory, I/O, and graphics chips for i, p, and zSeries machines. In the early days of the POWER4 program, he was a designer and microarchitect on the instruction sequencer unit (ISU) in the processor. In February of 2000, he assumed the role of department manager, responsible for processor core and chip verification of POWER4 and follow-on design points. Mr. Victor has filed 11 patents, one of which was recognized with a supplemental patent award. He has authored four technical publications, including a recent article in the IBM MicroNews on memory controller design. He received an IBM Outstanding Technical Achievement Award for chip design leadership in October 1997.

Bruce Wile   IBM Server Group, 2455 South Road, Poughkeepsie, New York 12603 (bwile@us.ibm.com). Mr. Wile, a Senior Technical Staff Member, is the IBM Server Group verification leader. In this role, Mr. Wile is responsible for verification methodology utilization on current projects, while also focusing on future technologies and verification investments. Mr. Wile has been in the verification field for 17 years and has worked on multiple server programs at IBM. He was the team leader for the S/390 Parallal Enterprise Server G4, as well as for previous generations. Mr. Wile received his B.S. degree from Pennsylvania State University in 1985. During his time with IBM, he has received multiple awards for his verification work, including an IBM Corporate Award, an IBM Outstanding Innovation Award, and an IBM Outstanding Technical Achievement Award. Mr. Wile also holds multiple patents in the verification field.