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Volume 40, Number 1, 1996
Terrestrial cosmic rays and soft errors |
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Table of contents:  HTML |
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Copyright info |
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Accelerated testing for cosmic soft-error rate |
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by J. F. Ziegler, H. P. Muhlfeld, C. J. Montrose, H. W. Curtis, T. J. O'Gorman, and J. M. Ross |
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This paper describes the experimental techniques which have been
developed at IBM to determine the sensitivity of electronic circuits to
cosmic rays at sea level. It relates IBM circuit design and modeling,
chip manufacture with process variations, and chip testing for SER
sensitivity. This vertical integration from design to final test and
with feedback to design allows a complete picture of LSI sensitivity to
cosmic rays. Since advanced computers are designed with LSI chips long
before the chips have been fabricated, and the system architecture is
fully formed before the first chips are functional, it is essential to
establish the chip reliability as early as possible. This paper
establishes techniques to test chips that are only partly functional
(e.g., only 1Mb of a 16Mb memory may be working) and can establish chip
soft-error upset rates before final chip manufacturing begins. Simple
relationships derived from measurement of more than 80 different chips
manufactured over 20 years allow total cosmic soft-error rate (SER) to be
estimated after only limited testing. Comparisons between these
accelerated test results and similar tests determined by "field testing"
(which may require a year or more of testing after manufacturing begins)
show that our experimental techniques are accurate to a factor of 2.
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