|
|
 |
|
 |
Volume 39, Numbers 1/2, 1995
IBM CMOS Technology |
|
Table of contents:  HTML |
|
|
Copyright info |
|
|
|
|
| |
|
CMOS scaling into the 21st century: 0.1 µm and beyond |
|
by Y. Taur, Y. J. Mii, D. J. Frank, H. S. Wong, D. A. Buchanan, S. J. Wind, S. A. Rishton, G. A. Sai-Halasz, and E. J. Nowak |
|
|
|
 |
|
This paper describes the design, fabrication, and characterization of
0.1-µm-channel CMOS devices with dual n+/p+ polysilicon gates on
35-Å gate oxide. A 2× performance gain over 2.5-V, 0.25-µm CMOS
technology is achieved at a power supply voltage of 1.5 V. In addition,
a 20× reduction in active power/circuit is obtained at a supply voltage <1 V
with the same delay as the 0.25-µm CMOS. These results
demonstrate the feasibility of high-performance and low-power
room-temperature 0.1-µm CMOS technology. Beyond 0.1 µm, a
number of fundamental device and technology issues must be examined:
oxide and silicon tunneling, random dopant distribution, threshold
voltage nonscaling, and interconnect delays. Several alternative
device structures (in particular, low-temperature CMOS and double-gate
MOSFET) for exploring the outermost limit of silicon scaling are
discussed.
|
|
|
|
|
