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Volume 39, Numbers 1/2, 1995
IBM CMOS Technology |
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Table of contents:  HTML |
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Copyright info |
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A 64Kb × 32 DRAM for graphics applications |
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by T. Sunaga, K. Hosokawa, S. H. Dhong, and K. Kitamura |
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A high-speed 2Mb CMOS DRAM with 32 data I/Os is described. A 0.6-µm
CMOS process with a single polysilicon layer, two levels of metal, and
substrate-plate trench-capacitor (SPT) memory cells is used to fabricate
the chip. It is designed to provide the wide data bandwidth required by
high-performance graphics applications. A 35-ns access time with an
80-ns cycle time has been demonstrated. The 32-bit data bus and the
high-speed feature achieve more than two times better graphics
performance than conventional dual-port memories. A sensing method with
a 2/3 VDD bit-line precharge voltage and a limited bit-line voltage
swing is exploited to optimize speed and power. The chip, which
operates on a 5-V power supply, dissipates 140 mA at the 80-ns cycle
time.
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