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Volume 39, Numbers 1/2, 1995
IBM CMOS Technology |
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Table of contents:  HTML |
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Copyright info |
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A half-micron CMOS logic generation |
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by C. W. Koburger III, W. F. Clark, J. W. Adkisson, E. Adler, P. E. Bakeman, A. S. Bergendahl, A. B. Botula, W. Chang, B. Davari, J. H. Givens, H. H. Hansen, S. J. Holmes, D. V. Horak, C. H. Lam, J. B. Lasky, S. E. Luce,
R. W. Mann, G. L. Miles, J. S. Nakos, E. J. Nowak, G. Shahidi, Y. Taur,
F. R. White, and M. R. Wordeman |
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During the early 1990s, half-micron lithography was demonstrated in 16Mb
DRAM fabrication. Utilization of this capability for CMOS logic devices
within IBM followed with a trio of programs, each with different
performance, density, feature list, and schedule. The first version
melded 3.3/3.6-V 16Mb DRAM MOSFET devices with an improved version of an
existing dense, planar, reliable multilevel back-end-of-line (BEOL)
metallization and wiring technology. Since it was built directly from
existing technologies, it was released quite quickly. A 3.3-V follow-on
technology was added several months later. This logic offering added
a local interconnect and a faster device. A second follow-on achieved
greater speed improvement, calling upon a 2.5-V power supply and very
tight channel-length control to obtain performances 50% above
previous-generation standards, at lower power.
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