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Volume 39, Numbers 1/2, 1995
IBM CMOS Technology |
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Table of contents:  HTML |
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Copyright info |
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Verity—A formal verification program for custom CMOS circuits |
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by A. Kuehlmann, A. Srinivasan, and D. P. LaPotin |
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In an effort to fully exploit CMOS performance, custom design techniques
are used extensively in commercial microprocessor design. However,
given the complexity of current-generation processors and the necessity
for manual designer intervention throughout the design process, proving
design correctness is a major concern. In this paper we discuss Verity,
a formal verification program for symbolically proving the equivalence
between a high-level design specification and MOS transistor-level
implementation. Verity applies efficient logic comparison techniques
which implicitly exercise the behavior for all possible input
patterns. For a given register-transfer level (RTL) system model, which
is commonly used in present-day methodologies, Verity validates the
transistor implementation with respect to functional simulation and
verification performed at the RTL level.
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