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Volume 39, Numbers 1/2, 1995
IBM CMOS Technology |
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Table of contents:  HTML |
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Copyright info |
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Overview of gate linewidth control in the manufacture of CMOS logic chips |
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by D. G. Chesebro, J. W. Adkisson, L. R. Clark, S. N. Eslinger, M. A. Faucher, S. J. Holmes, R. P. Mallette, E. J. Nowak, E. W. Sengle, S. H. Voldman, and T. W. Weeks |
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This paper is an overview of the methods used at the Burlington facility
of the IBM Microelectronics Division to improve channel-length tolerance
control in the manufacture of CMOS logic chips. We cover aspects of 1)
the impact of channel-length control on chip performance, yield, and
reliability; 2) our use of an electrical linewidth monitor which
permits high-volume, accurate measurements to quantify polysilicon gate
linewidth variability and its improvements; and 3) our efforts to
reduce photolithographic and etching contributions to the linewidth
variability.
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