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Volume 39, Numbers 1/2, 1995
IBM CMOS Technology |
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Table of contents:  HTML |
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Copyright info |
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Architectural timing verification of CMOS RISC processors |
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by P. Bose and S. Surya |
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We consider the problem of verification and testing of architectural
timing models ("timers") coded to predict cycles-per-instruction (CPI)
performance of advanced CMOS superscalar (RISC) processors. Such timers
are used for pre-hardware performance analysis and prediction. As such,
these software models play a vital role in processor performance tuning
as well as application-based competitive analysis, years before actual
product availability. One of the key problems facing a designer,
modeler, or application analyst who uses such a tool is to understand how
accurate the model is, in terms of the actual design. In contrast to
functional simulators, there is no direct way of testing timers in the
classical sense, since the "correct" execution time (in cycles) of a
program on the machine model under test is not directly known or
computable from equations, truth tables, or other formal specifications.
Ultimate validation (or invalidation) of such models can be achieved
under actual hardware availability, by direct comparisons against
measured performance. However, deferring validation solely to that stage
would do little to achieve the overall purpose of accurate pre-hardware
analysis, tuning, and projection. We describe a multilevel validation
method which has been used successfully to transform evolving timers into
highly accurate pre-hardware models. In this paper, we focus primarily
on the following aspects of the methodology: a) establishment of
cause-effect relationships in terms of model defects and the associated
fault signatures; b) derivation of application-based test loop kernels to
verify steady-state (periodic) behavior of pipeline flow, against
analytically predicted signatures; and c) derivation of synthetic test
cases to verify the "core" parameters characterizing the pipeline-level
machine organization as implemented in the timer model. The basic tenets
of the theory and its application are described in the context of an
example processor, comparable in complexity to an advanced member of the
PowerPC™ 6XX processor family.
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