|
|
 |
|
 |
Volume 39, Numbers 1/2, 1995
IBM CMOS Technology |
|
Table of contents:  HTML |
|
|
Copyright info |
|
|
|
|
| |
|
Digital delay line clock shapers and multipliers |
|
by R. A. Bechade and R. M. Houle |
|
|
|
 |
|
Two digital techniques have been developed to generate an internal clock
signal from an external reference clock supplied to a microprocessor.
The first method constitutes a clock shaper circuit that produces an
output clock that has a 50% duty cycle regardless of the duty cycle of
the input reference clock. The second technique generates an internal
clock that is an N/2 multiple of the frequency of the input clock, where
N is an integer greater than 1. Both methods are entirely digital and
are independent of process and temperature variations. Their accuracy
limits are determined by the technology. Both circuits are described and
their results compared.
|
|
|
|
|
