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Author bios
Eric Adler
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (U6326 at BTVLABVM). Dr. Adler received a B.S.
degree from City College of New York in 1959, and a Ph.D. in physics
from Columbia University in 1964. After one year as a postdoctoral
fellow at the IBM Thomas J. Watson Research Center, he joined the
faculty at the City College of New York, where he was an assistant
professor of physics from 1965 to 1968. In 1968, he joined what is
now the IBM Microelectronics Division in Essex Junction, Vermont, where
he is currently a senior engineer. His early work at IBM was in
reliability of DRAM and EEPROM devices. Since 1978 he has worked on
device design and process integration for 1Mb and 16Mb DRAM and logic
technologies. He is a member of IEEE and a recipient of an IBM
First-Level Patent Achievement Award.
John K. DeBrosse
IBM Microelectronics Division, East Fishkill facility, Route 52,
Hopewell Junction, New York 12533 (JDEBROSS at FSHVMFK1). Mr.
DeBrosse received his B.S.E.E. (1983) and M.S.E.E. (1984) from Purdue
University. Since that time he has worked on cell design and early
technology development for the IBM 4Mb, 16Mb, 64Mb, and 256Mb DRAM
programs. He is currently a circuit designer on the 256Mb program.
Stephen F. Geissler
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (A928471 at BTVLABVM). Mr. Geissler is currently an
advisory engineer in advanced CMOS logic development. He received a
B.S. from the Rochester Institute of Technology in 1981 and an M.E.
from Cornell University in 1982. He then joined IBM at Essex Junction,
Vermont, where he has since been involved in device design and process
integration for the development of 1Mb and 16Mb DRAM technologies. He
is currently involved in the development of an advanced CMOS logic
technology.
Steven J. Holmes
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (SHOLMES at BTVLABVM). Dr. Holmes received a
B.S. in chemistry from Yale University in 1979, and a Ph.D. in
chemistry from the Massachusetts Institute of Technology in 1983. After
a one-year postdoctoral fellowship at Purdue University, he joined a
lithography development project at IBM in Essex Junction, Vermont. For
the last ten years he has worked on the development and implementation
of DUV (deep ultraviolet) lithography for semiconductor manufacturing.
Initial applications of DUV lithography were focused on 1Mb and 16Mb
DRAM devices, with more recent work directed toward gate conductor
lithography for advanced logic semiconductor chips.
Mark D. Jaffe
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (MJAFFE at BTVLABVM). Dr. Jaffe received a B.S.E. in
electrical engineering in 1984, an M.S.E. in 1986, and a Ph.D. in 1989,
all from the University of Michigan. His thesis work was on the
effects and applications of coherent strain in III-V semiconductors. He
joined the IBM General Technology Division in January of 1989 and has
been working since in the area of CMOS DRAM device and process design.
Among other things, he has worked on DRAM cell design, DRAM process
improvements for improved retention time, analysis of electrostatic
discharge protection devices, CMOS latch-up, and gated diode leakage
phenomena associated with DRAM trench storage capacitors. Dr. Jaffe is
a member of the IEEE, Tau Beta Pi, and Eta Kappa Nu.
Jeffrey B. Johnson
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (JBJ at BTVLABVM). Dr. Johnson received the B.S.
degree in electrical engineering from the University of Kansas,
Lawrence, in 1984 and the Ph.D. degree in electrical and computer
engineering from Carnegie Mellon University, Pittsburgh, Pennsylvania,
in 1988. Since 1988 he has worked for IBM at Essex Junction, Vermont,
in the area of CAD software development and application.
Charles W. Koburger III
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (U7402 at BTVLABVM). Dr. Koburger joined the IBM
General Technology Division in Essex Junction in 1978, having received
his Ph.D. in materials engineering from the Rensselaer Polytechnic
Institute, Troy, New York. He has worked in process technology from
that time to the present. Projects have included tungsten polycide word
lines for DRAM and logic applications, shallow diffusion technology,
and storage and isolation trench processing for DRAMs. Most recently,
Dr. Koburger has been the lead process integrator for high-performance
half-micron logic devices.
Jerome B. Lasky
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (A742573 at BTVLABVM). Dr. Lasky received his
Ph.D. in solid state physics from the University of Wisconsin in 1976.
He joined IBM at Essex Junction in 1978. From 1978 to 1986 he worked in
a base technology group on rapid annealing of junctions, silicide
formation, and silicon-on-insulator laser annealing. From 1982 to 1984
he led the group which developed a bonding and etch-back method for
forming silicon-on-insulator. In 1986 he joined the group which
developed IBM's initial 16Mb chip. His responsibilities included FEOL
process integration, with direct responsibility for device process
integration, silicides, and retention-time improvement. Since 1993 he
has been principal process integration engineer for the 16Mb program.
He has published twelve papers and holds fourteen patents in
semiconductor processing and device effects.
Brian Lloyd
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (BLLOYD at BTVVMOFS). Mr. Lloyd received his B.S. in
physics from Earlham College, Richmond, Indiana, in 1964. He completed
graduate studies at Amherst College, Amherst, Massachusetts, and the
University of Vermont, Burlington, in statistical molecular physics. He
joined IBM at Essex Junction in 1980 and is currently involved in a
wide variety of projects, including metal contamination monitoring,
in-line metrology, and retention time and variable retention time
modeling.
Glen L. Miles
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (GMILES at BTVVMOFS). Mr. Miles received a B.S. in
chemical engineering in 1984 from Yale University, and an M.S. in
mechanical engineering in 1990 from the Rensselaer Polytechnic
Institute, Troy, New York. He joined IBM in 1984 and has been involved
in silicide and hot-process engineering in CMOS DRAM and logic
technologies.
James S. Nakos
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (JNAKOS at BTVLABVM). Dr. Nakos received a B.S. in
physics from the University of Massachusetts at Amherst in 1977
and a Ph.D. in materials science from the Massachusetts
Institute of Technology in 1988. He joined IBM in Essex Junction,
Vermont, in 1988 and was involved in the development of the 16Mb,
0.5-µ m DRAM program. Currently he is an advisory engineer involved in
the development of the process line for IBM's 0.25-µ m logic program.
His professional interests include silicide technology and the
implementation of rapid thermal processing in manufacturing. Dr. Nakos
holds five patents and has published a number of technical papers.
Wendell P. Noble, Jr.
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (NOBLE at BTVLABVM). Dr. Noble received the B.S.
degree in engineering physics from the University of Maine in 1961, the
M.S. degree in physics from the University of New Hampshire in 1964,
and the Ph.D. degree in solid state science from
Pennsylvania State University in 1967. From 1966 to 1968 he was a member
of the technical staff at the Sprague Electric Company, where he worked
on MOS device physics. In 1968 he joined IBM in Essex Junction,
Vermont, where he is now a senior technical staff member working on the
development of advanced FET memory devices. Dr. Noble is a member
of the IEEE, the American Physical Society, and the Electrochemical
Society.
Steven H. Voldman
IBM Microelectronics Division, Burlington facility, Essex Junction,
Vermont 05452 (A108501 at BTVLABVM). Dr. Voldman is an advisory
engineer/scientist at the IBM Microelectronics semiconductor
facility in Essex Junction. He received his B.S. in engineering science
in 1979 from the University of Buffalo, and an M.S. in electrical
engineering in 1981 and the Electrical Engineer degree in 1982 from the
Massachusetts Institute of Technology. In addition, he received an M.S.
degree in engineering physics in 1986 and a Ph.D. in electrical
engineering in 1991 from the University of Vermont under the IBM
Resident Study Fellow program. In 1982, Dr. Voldman joined IBM in Essex
Junction, Vermont, developing bipolar SRAM, and CMOS SRAM/DRAM alpha-particle soft-error-rate (SER) Monte Carlo simulations. He joined the
IBM 4Mb DRAM development team in 1984, working on alpha-particle and
cosmic-ray effects on DRAMs and SRAMs, wiring capacitance simulation,
gate-induced drain leakage, and DRAM retention time and CMOS latch-up.
Dr. Voldman joined the IBM 16Mb DRAM and 0.5- and 0.25-µ m advanced
FET logic development team in 1991; he has worked on MOSFET drain
engineering, hot electrons, line width control, and currently,
electrostatic discharge (ESD). He is a member of the EOS/ESD Symposium
Technical Program Committee and an EOS/ESD Symposium session moderator.
He has authored and coauthored more than 30 papers and is a recipient
of the IBM Second Level Invention Achievement Award. He is also an
external ESD consultant for IBM Analytical Services.
Michael Armacost
IBM Microelectronics Division, East Fishkill facility, Route 52,
Hopewell Junction, New York 12533 (MARMACOS at FSHVMFK1). Mr.
Armacost is a process engineer in the IBM Microelectronics Division at
Hopewell Junction, New York. He is responsible for selective dry-oxide
etch processing in the 64MB and 256MB DRAM development programs at the
Semiconductor Research and Development Center. He has six years of
experience in dry etch processing for advanced semiconductor
applications. Mr. Armacost holds a B.A. in chemistry from Western
Maryland College, Westminster, Maryland, and an M.S. in chemical
engineering from Clarkson University, Potsdam, New York.
Richard Ferguson
IBM Microelectronics Division, East Fishkill facility, Route 52,
Hopewell Junction, New York 12533 (FERGRICH at FSHVMFK1). Dr.
Ferguson received his B.S. in electrical engineering from Duke
University in 1985. He received his M.S. in 1987 and his Ph.D. in
1991 from the University of California at Berkeley, where he worked
on the modeling and simulation of advanced resist processes for
optical lithography. Since 1991, he has been working at the IBM
Semiconductor Research and Development Center in Hopewell Junction, New
York, in advanced lithography
development for product applications in DRAM memory and
logic.
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