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Catagories:
Asynchronous Synthesis
Dynamic Logic Synthesis
FPGA
Gain Based Synthesis
Interconnect and Buffer Planning
Logic
Logic Synthesis
Low Power
Placement Driven Synthesis
Regularity

SOI Design And Analysis

Gain Based Synthesis

Wavefront Technology Mapping (DATE 1999) Technology mapping that is optimal for delay.
Gate Sizing Using Geometric Programming, David Kung, Prabhakar Kudva International Workshop on Logic Synthesis (IWLS 1998)
Gate Sizing Selection for Standard Cell Libraries. F. Beeftink, P. Kudva, D. Kung, L. Stok. International Conference on Computer Aided Design, ICCAD 1998
F. Beeftink, P. Kudva, D. Kung, R. Puri, and L. Stok, Combinatorial Cell Design for CMOS Libraries, VLSI Integration, February, 2000.
D. Kung and R. Puri, Optimal P/N Width Ratio Selection for Standard Cell Libraries, ACM/IEEE International Conference on CAD (ICCAD), 1999.
D, Kung, A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries, ICCAD 98, p 352 - 355.
Placement Driven Synthesis
A. Handa, R. Puri and J. Gu, An Efficient Steiner Tree based approach for Multilayer Routing, Proceedings of Maryland Conference on Advanced Routing of Electronic Modules, September 1995.
D. Montuno, G. Wilson, R. Puri, A. Marks, T. Montor, P.C. Wong, P. Quesnel, M. Rizvi, C. Goemans, C. Zhang, B. Stacey and J. Davies, Functional/Physical Codesign, Proceedings of Canadian Conference on Electrical and Computer Engineering, September 1995.
Transformational Placement and Synthesis - Wilm Donath, Prabahakar Kudva, Leon Stok, Paul V illarrubia, Lakshmi Reddy, Andrew Sullivan, Kanad Chakraborty. Design Automation and Test i n Europe (DATE 2000)
Performance Driven Optimization of Network Length in Physical Placement, DAC 1999. A method for changing the placement of groups of circuits so as to reduce delay.
Performance Driven Optimization of Network Length in Physical Placement - Wilm Donath, Prah bakar Kudva, Lakshmi Reddy International Confercen on Computer Design (ICCD 1999)
A. H. Farrahi, "Estimation and Removal of Routing Congestion", Proc. of Int'l Workshop on System-Level Interconnect Prediction, pp. 149, April 2000, San Diego, CA.
Asynchronous Synthesis
High Level Design of Asynchronous Systems using ACK, Hans Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva. Proceedings of the Symposium on Advanced Research in Asynchronous Circuits and Systems 00, IEEE Computer Society Press.
Asynchronous Transpose Matrix Architectures, Jose Tierno and Prabhakar Kudva. Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors (ICCD), October 1997.
Synthesis of Distributed Burst-mode Controllers, Prabhakar Kudva and Ganesh Gopalakrishnan. Proceedings of the IEEE/ACM Design Automation Conference, June 1996. Pages 63-66. IEEE Computer Society Press.
Synthesis of Hazard-free Customized Complex Gate Circuits Under Multiple-Input-Change, Prabhakar Kudva and Hans Jacobson and Ganesh Gopalakrishnan and Steven Nowick. Proceedings of the IEEE/ACM Design Automation Conference, June 1996. pages 67-71. IEEE Computer Society Press.
Performance Analysis and Optimization of Asynchronous Circuits, Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella. Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors (ICCD), October 1994, pages 221-225.
Testing Two-phase Transition Signalling Based Self-Timed Circuits in a Synthesis Environment, Prabhakar Kudva, Venkatesh Akella. Proceedings of the Seventh International Symposium on High-Level Synthesis 1994. IEEE Computer Society Press, pages 104-111, IEEE Computer Society Press.
A Technique to Estimate Power in Asynchronous Circuits, Prabhakar Kudva, Venkatesh Akella. Proceedings of the Symposium on Advanced Research in Asynchronous Circuits and Systems 94, pages 166-175. IEEE Computer Society Press.
An Asynchronous High Level Synthesis System Targeted at Interacting Burst-Mode Controllers, Prabhakar Kudva, Ganesh Gopalakrishnan, Venkatesh Akella. Proceedings of the International Conference on Hardware Description Languages (CHDL 95).
Peephole Optimization of Asynchronous Circuits, Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand. Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors (ICCD) 94, October 1994 pages 471-474.
Hazard-non-increasing gate-level optimization algorithms, ICCAD 92, pages 631-634. Given an unoptimized logic without hazards, how to generate a multi-level optimized implementation.
Path Sensitization in Hazard-free Circuits, TAU 95. Pages are in reverse order with last page first. In hazard-free circuits many paths can be eliminated from timing analysis.
R. Puri and J. Gu, Area Efficient Synthesis of Asynchronous Circuits, Proceedings of IEEE International Conference on Computer Design (ICCD), October 1994.
A Modular Partitioning Approach for Asynchronous Circuit Synthesis, R. Puri and J. Gu, IEEE Transactions on CAD, August 1995, pages 961-973. How to partition a state transition graphs into partitions small enough for existing asynchronous synthesis algorithms.
R. Puri and J. Gu, A Modular Partitioning Approach for Asynchronous Circuit Synthesis, Proceedings of 31st ACM/IEEE Design Automation Conference (DAC), June 1994, pages 63-69.
R. Puri and J. Gu, A Divide-and-Conquer Approach for Asynchronous Interface Synthesis, Proceedings of 7th ACM/IEEE International High-Level Synthesis Symposium, May 1994, pages 118-125.
R. Puri and J. Gu, Interconnecting Asynchronous Control Modules, Proceedings of Canadian Conference on VLSI, November 1993, pages 3B7-3B12.
R. Puri and J. Gu, An Efficient State Minimization Algorithm for Finite State Machines, Proceedings of ACM/IEEE International Workshop on Logic Synthesis (IWLS), May 1993, pages p5c.1-p5c.10.
R. Puri and J. Gu, Signal Transition Graph Constraints for Speed-independent Circuit Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems, May 1993, pages 1686-1689.
R. Puri, Design of Asynchronous VLSI Circuits, Invited Chapter in John Wiley & Sons Encyclopedia of Electrical and Electronics Engineering, Volume 1, 1999.
An Efficient Algorithm to Search for Minimal Closed Covers in Sequential Machines IEEE Transactions on CAD, June 1993, pages 737-745. Used for state minimization.
R. Puri and J. Gu, Microword Length Minimization in Microprogrammed Controller Synthesis, IEEE Transactions on CAD (TCAD), Volume 12, Number 10, October 1993, pages 1449-1457.
J. Gu and R. Puri, Asynchronous Circuit Synthesis with Boolean Satisfiability, IEEE Transactions on CAD (TCAD), Volume 14, Number 9, September 1995, pages 961-973.
R. Puri and J. Gu, Persistency and Complete State Coding Constraints in Signal Transition Graphs, International Journal of Electronics, Volume 75, Number 5, November 1993, pages 933-940.
Logic
R. Puri and J. Gu, An Efficient Algorithm for Microword Length Minimization, Proceedings of 29th ACM/IEEE Design Automation Conference (DAC), June 1992, pages 651-656.
R. Puri and J. Gu, Searching For a Minimal Finite State Automaton, Proceedings of Third IEEE International Conference on Tools with Artificial Intelligence, November 1991, pages 416-423.
R. Puri and M. M. Hasan, PLASMA : An FSM Design Kernel, Proceedings of Third IEEE International ASIC Conference, September 1990, pages 162.1-162.4.
D.Y.Montuno, R. Puri, B. Stacey, Multi-Disciplinary Analysis Using Constraint Logic Programming with Relational Interval Arithmetic, ACM International Logic Programming Symposium, October 1997.
A BDD SAT Solver for Satisfiability: A Case Study, R. Puri and J. Gu, Annals of Mathematics, 1996, Number 9, pages 1-23. Boolean satisfiability solver especially for asynchronous synthesis problems.
Dynamic Logic Synthesis
R. Puri, A. Bjorksten, and T. E. Rosser, Logic Optimization by Output Phase Assignment in Dynamic Logic Synthesis ACM/IEEE International Conference CAD (ICCAD), 1996. Output phase assignment for minimum area duplication in dynamic logic synthesis to obtain logic with inverters at primary inputs/outputs only.
R. Puri, Design Issues in Mixed Static-Domino Circuit Implementations, IEEE Intl. Conf. on Computer Design (ICCD), 1998.
R. Puri and K. L. Shepard, Timing Issues in Static-Dynamic Synthesis, ACM Workshop on Timing issues in spec. and synthesis of digital systems (TAU), 1997.
SOI Design And Analysis
R. Puri and C. T. Chuang, Hysteresis Effect in Pass-Transistor based Partially Depleted SOI CMOS Circuits, IEEE Journal of Solid State Circuits (JSSC), April 2000, pages 625-631.
R. Puri, C. T. Chuang, M. B. Ketchen, M. M. Pelella, and M. G. Rosenfield, Floating Body Effects in Low-Temperature Partially Depleted SOI CMOS Circuits, IEEE Journal of Solid State Circuits (JSSC), Februray 2001.
C. T. Chuang, R. Puri, J.B. Kuang, and R. Joshi, High-Performance SOI Digital Design: from Devices to Circuits, Invited Short Course in IEEE VLSI Circuits Synposium, 2001, Kyoto.
C. T. Chuang, R. Puri, K. Bernstein, Effect of Gate-to-Body Tunneling current on PD/SOI CMOS Circuits, International Conference on Solid-State Devices and Materials (SSDM) 2001.
K. A. Jenkins, R. Puri, C. T. Chuang, and F.L.Pasavento, Measurement of History Effect in PD/SOI Single Ended CPL Circuits, IEEE Intl Conference on SOI, 2001.
C. T. Chuang, R. Puri, and R. Joshi, SOI Circuit Design for High-Performance CMOS Micro-processors, International Solid-State Circuits Conference (ISSCC), 2001 Invited Tutorial.
R. Puri, C. T. Chuang, M. B. Ketchen, M. M. Pelella, and M. G. Rosenfield, On the Temperature Dependence of Hysteresis Effect in Floating-Body Partially Depleted SOI CMOS Circuits, International Conference on Solid-State Devices and Materials (SSDM) 2000.
M. M. Pelella, J. G. Fossum, C. T. Chuang, O. A. Torreiter, H. Schettler, R. Puri, M. B. Ketchen, and M. G. Rosenfield, Low-Temperature DC Bipolar Effect in PD/SOI MOSFETs with Floating Bodies, IEEE Intl. SOI Conference 2000.
R. Puri and C. T. Chuang, SOI Digital Circuits: Design Issues, IEEE Intl. Conference on VLSI Design, Invited tutorial, 2000.
C. T. Chuang and R. Puri, Design Perspective for SOI CMOS Microprocessors, Year 2000 International Symposium on Key Technologies for Future VLSI Systems (Invited talk), Tokyo.
R. Puri and C. T. Chuang, Hysteresis Effect in Floating Body Partially Depleted SOI CMOS Domino Circuits, ACM/IEEE Intl. Symposium on Low Power Electronics Design (ISLPED), 1999.
C. T. Chuang and R. Puri, SOI Digital CMOS VLSI - A Design Perspective, ACM/IEEE Design Automation Conference (DAC), 1999 (Invited talk in a special session on Technology Directions).
C. T. Chuang and R. Puri, Digital CMOS VLSI Design in SOI, Invited talk in IEEE Intl. Symposium on VLSI Technology, Systems, and Applications, 1999.
R. Puri and C. T. Chuang, Hysteresis Effect in Pass-Transistor based Partially Depleted SOI CMOS Circuits, IEEE Intl. SOI Conference, 1998.
FPGA
Integrated Decomposition and Covering with Area vs. Running Time Trade-off in FPGA Technology Mapping (submitted to DAC 1999) Uses a fast covering algorithm to guide decomposition and performs BDD variable ordering targeting LUT minimization.
A. H. Farrahi, M. Sarrafzadeh, "An FPGA Technology Mapper With Fast and Accurate Prediction" IBM Research Report, 1997.
A. H. Farrahi, M. Sarrafzadeh, TDD: A Technology Dependent Decomposition Algorithm for LUT-Based FPGAs, Proc. of the IEEE Int'l ASIC Conference, pp. 206-209, Sept. 1997, Portland, OR. Uses a fast covering algorithm to guide decomposition phase rather than using simple cost functions.
A. H. Farrahi, M. Sarrafzadeh, "Complexity of the Lookup-Table Minimization Problem for FPGA Technology Mapping", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13(11) pp. 1319--1332, Nov. 1994.
A. H. Farrahi and M. Sarrafzadeh, "FPGA Technology Mapping for Power Minimization", Proc. of Intl. Workshop on Field Programmable Logic and Applications, pp. 66-77, September 1994, Prague.
A. H. Farrahi, M. Sarrafzadeh, "On Lookup-Table Minimization for FPGA Technology Mapping", In Int'l Workshop on Field Programmable Logic Arrays, pp. Feb. 1994, Berkeley, CA.
Low Power
Inaccuracies in Gate-Level Power Estimation (RC 20520, August 1996) Experiments on the error in power estimation due to logic synthesis, PD, unknown inputs, glitches, and ignoring some electrical effects.
Geo_Part: A System Partitioning Algorithm to Maximize Sleep Time (Submitted to IEEE Trans. on Computers) Partitioning a system based on the activity patterns on its elements, in order to maximize total sleep time.
A. H. Farrahi, D. T. Lee, M. Sarrafzadeh, Two-Way and Multiway Partitioning of a Set of Intervals for Clique-Width Maximization, Algorithmica, Vol. 23, Issue 3, pp. 187-210, 1999. A hardware system is partitioned so as to minimize power. The approach is based on analyzing intervals of activity and inactivity for various elements of the system.
On the Power of Logic Resynthesis, W. L. Lin, A. H. Farrahi, M. Sarrafzadeh, SIAM J. on Computing, Vol. 29, No. 4, pp. 1257 - 1289.
Power Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microproc essors. David M. Brooks, Pradip Bose, Stanley E. Schuster, Hans Jacobson, Prabhakar N. Kudv a, Alper Byukosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta and Peter W. Cook. I EEE Micro Vol 20 No 6. Nov/Dec 2000
Mixed Multi-Threshold-voltage DCVS Circuit Styles and Strategies for Low Power Design. W.Ch en et. al to appear ISLPED 01
A. H. Farrahi, C. Chen, M. Sarrafzadeh, G. Tellez, "Activity-Driven Clock Design", To appear in IEEE Transactions on on Computer-Aided Design of Integrated Circuits and Systems.
A. H. Farrahi, G. E. Tellez, M. Sarrafzadeh, Exploiting Sleep Mode for Memory Partitioning and Other Applications, VLSI Design Journal, Vol 7, No 3, pp.271-287, 1998. Formulates the problem of partitioning a circuit based on the activity patterns of its elements for power optimization. Shows that the problem is NP-complete, and discusses a couple of variations.
G. E. Tellez, Amir Farrahi, and M. Sarrafzadeh, "Activity-Driven Clock Design for Low Power Circuits", Proc. IEEE Int'l Conf. on Computer-Aided Design, pp. 62-65, Nov. 1995, San Jose, CA.
A. Farrahi, M. Sarrafzadeh, "Geo_Part: A System Partitioning Algorithm to Maximize Sleep Time", Submitted to IEEE Trans. on Computers.
A. H. Farrahi and M. Sarrafzadeh, "System Partitioning to Maximize Sleep Time", Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design, pp. 452-455, Nov. 1995, San Jose, CA.
A. H. Farrahi, G. E. Tellez, and M. Sarrafzadeh, "Memory Segmentation to Exploit Sleep Mode Operation", Proc. of ACM/IEEE Design Automation Conference, June 1995, pp. 36-41. San Francisco, CA.
Interconnect and Buffer Planning
J. Cong, L. He, C.-K. Koh, and Z. Pan, Interconnect Sizing and Spacing with Consideration of Coupling Capacitance, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2001.
J. Cong, T. Kong, and Z. Pan, Buffer Block Planning for Interconnect Planning and Prediction, IEEE Trans. on Very Large Scale Integration Systems, 2001.
J. Cong and Z. Pan, " Interconnect Performance Estimation Models for Design Planning , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001.
J. Cong, Z. Pan and P.V. Srinivas, " Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization , Proc. Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 30 - Feb. 2, 2001, Pacifico Yokohama, Japan.
J. Cong, Z. Pan and P.V. Srinivas, " Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization , Proc. ACM/ACM TAU, Dec. 4-5, 2000, Austin.
C.-C. Chang, J. Cong, Z. Pan, and X. Yuan, " Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization , Proc. SRC Techcon Conference, September 21-3, 2000, Phoenix.
J. Cong, Z. Pan, and P.V. Srinivas, " Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization , Proc. SRC Techcon Conference, September 21-3, 2000, Phoenix.
J. Cong, T. Kong, and Z. Pan, " Buffer Block Planning for Interconnect-Driven Floorplanning ", Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, November, 1999.
J. Cong and Z. Pan, " Interconnect Estimation and Planning for Deep Submicron Designs", Proc. ACM/IEEE 36th Design Automation Conf., June 20-5, 1999, New Orleans.
J. Cong and Z. Pan, " Interconnect Delay and Area Estimation for Multiple-Pin Nets ", Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 8-9, 1999, Monterey.
J. Cong and Z. Pan, " Interconnect Delay Estimation Models for Synthesis and Design Planning ", Proc. Asian and South Pacific Design Automation Conference (ASP-DAC), January 18-21, 1999.
J. Cong and Z. Pan, " Interconnect Delay Estimation Models for Logic and High Level Synthesis ", Proc. SRC Techcon Conference, September 9-11, 1998, Las Vegas, (Best Paper In Session).
J. Cong and Z. Pan, " Interconnect Performance Estimation Models for Synthesis and Design Planning ", ACM/IEEE Int'l Workshop on Logic Synthesis, June, 1998.
J. Cong, L. He, C.-K. Koh, and Z. Pan, " Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance ", Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, November, 1997.
J. Cong, L. He, K.-Y. Khoo, C.-K. Koh, and Z. Pan, " Interconnect Design for Deep Submicron ICs", Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, November, 1997, (Invited Tutorial).
J. Cong, L. He, C.-K. Koh, and Z. Pan, " Interconnect Sizing and Spacing with Consideration of Coupling Capacitance ", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2001. ,
Regularity
Regularity Driven Logic Synthesis (ICCAD 2000, San Jose, CA) Preserve regular structures during logic synthesis by means of regularity signatures.
Efficient Logic Optimization Using Regularity Extraction (ICCD 2000, Austin, TX) Extract regular structures from a design and use this information to speed up logic optimization by duplicating identical parts.
Logic Synthesis
A. H. Farrahi, D. J. Hathaway, M. Wang, M. Sarrafzadeh, Quality of EDA CAD Tools: Definitions, Metrics and Directions Invited paper, Proc. of the IEEE Int'l Symp. on Quality of Electronic Design, March 2000, San Jose, CA.
BooleDozer: Logic Synthesis for ASICs (IBM Journal of R&D, July 1996) Overview paper of the BooleDozer logic synthesis system.
Algorithms for Incremental Synthesis, (RC 20352) Functional correspondence, structural correspondence, and the logic reuse algorithms.
Efficient Use of Large Don't Cares in High-Level and Logic Synthesis, ICCAD 95, pages 272-278. How to extract don't cares in high level synthesis and how to take advantage of them in logic synthesis.
Be careful with Don't Cares, ICCAD 95, pages 83-86. If you divide a design into partitions, then synthesize each partition correctly, and put the implemented partitions together, will the result be correct?
Don't Cares in Synthesis: Theoretical Pitfalls and Practical Solutions (RC 20127, September 95) Combination of the above two conference papers.
Improving Initialization through Reversed Retiming, EDTC 95, pages 150-154. How to find new register reset values for retimed circuits.
Incremental Synthesis, ICCAD 94, pages 14-18. Describes how to reuse an old implementation when a designer changes his specification.
In the Driver's Seat of BooleDozer, ICCD 94, pages 518-521. Pages are in reverse order with last page first. How designers can control BooleDozer synthesis.
Timing Verification and Optimization for the PowerPC Processor Family, ICCD 94, pages 390-393. Pages are in reverse order with last page first.
Microword Length Minimization in Microprogrammed Controller Synthesis, IEEE Transactions on CAD, October 1993, pages 1449-1457.
False Loops through Resource Sharing, ICCAD 92, pages 345-348. Unconstrained high-level synthesis tends to create false loops, causing difficulties for timing analysis. The false loops can be avoided without compromising too much in quality of logic.
BDDMAP: a technology mapper based on a new covering algorithm, DAC 92, pages 484-487. Rule based mapping combined with BDD-based functional mapping.