A. H. Farrahi, M. Sarrafzadeh, "Complexity of the Lookup-Table
Minimization Problem for FPGA Technology Mapping", IEEE Trans. on
Computer-Aided Design of Integrated Circuits and Systems, Vol. 13(11)
pp. 1319--1332, Nov. 1994.
A. H. Farrahi and M. Sarrafzadeh, "FPGA Technology Mapping for Power
Minimization", Proc. of Intl. Workshop on Field Programmable Logic and
Applications, pp. 66-77, September 1994, Prague.
A. H. Farrahi, M. Sarrafzadeh, "On Lookup-Table Minimization for FPGA
Technology Mapping", In Int'l Workshop on Field Programmable Logic
Arrays, pp. Feb. 1994, Berkeley, CA.
Power Aware Microarchitecture: Design and Modeling Challenges for
Next-Generation Microproc essors. David M. Brooks, Pradip Bose,
Stanley E. Schuster, Hans Jacobson, Prabhakar N. Kudv a, Alper
Byukosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta and
Peter W. Cook. I EEE Micro Vol 20 No 6. Nov/Dec 2000
Mixed Multi-Threshold-voltage DCVS Circuit Styles and Strategies for
Low Power Design. W.Ch en et. al to appear ISLPED 01
A. H. Farrahi, C. Chen, M. Sarrafzadeh, G. Tellez, "Activity-Driven
Clock Design", To appear in IEEE Transactions on on Computer-Aided
Design of Integrated Circuits and Systems.
A. H. Farrahi, G. E. Tellez, M. Sarrafzadeh,
Sleep Mode for Memory Partitioning and Other Applications, VLSI Design
Journal, Vol 7, No 3, pp.271-287, 1998. Formulates the problem of partitioning
a circuit based on the activity patterns of its elements for power optimization.
Shows that the problem is NP-complete, and discusses a couple of variations.
G. E. Tellez, Amir Farrahi, and M. Sarrafzadeh, "Activity-Driven Clock
Design for Low Power Circuits", Proc. IEEE Int'l Conf. on
Computer-Aided Design, pp. 62-65, Nov. 1995, San Jose, CA.
A. Farrahi, M. Sarrafzadeh, "Geo_Part: A System Partitioning Algorithm
to Maximize Sleep Time", Submitted to IEEE Trans. on Computers.
A. H. Farrahi and M. Sarrafzadeh, "System Partitioning to Maximize
Sleep Time", Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design,
pp. 452-455, Nov. 1995, San Jose, CA.
A. H. Farrahi, G. E. Tellez, and M. Sarrafzadeh, "Memory Segmentation
to Exploit Sleep Mode Operation", Proc. of ACM/IEEE Design Automation
Conference, June 1995, pp. 36-41. San Francisco, CA.
Be careful with Don't Cares, ICCAD 95, pages 83-86. If you
divide a design into partitions, then synthesize each partition correctly,
and put the implemented partitions together, will the result be correct?
Loops through Resource Sharing, ICCAD 92, pages 345-348.
Unconstrained high-level synthesis tends to create false loops, causing
difficulties for timing analysis. The false loops can be avoided without
compromising too much in quality of logic.